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Mask medeleg correctly
author
Andrew Waterman
<andrew@sifive.com>
Fri, 3 Nov 2017 02:15:42 +0000
(19:15 -0700)
committer
Andrew Waterman
<andrew@sifive.com>
Fri, 3 Nov 2017 02:15:42 +0000
(19:15 -0700)
riscv/processor.cc
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diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 203394b679de0e3749d1ca7e96f943e3b07a26a6..d23c1ea69f7a2b3aa6b61991e91730f50abf06bb 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-360,9
+360,13
@@
void processor_t::set_csr(int which, reg_t val)
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT
- | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT
- | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT;
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}