projects / riscv-isa-sim.git / history
| 2018-03-03 | Andrew Waterman | Implement clearing-misa.C-while-PC-is-misaligned proposal | blob | commitdiff | raw |
| 2015-03-13 | Andrew Waterman | Update to new privileged spec | blob | commitdiff | raw | diff to current |
| 2015-02-08 | Andrew Waterman | Use xlen, not xprlen, to refer to x-register width | blob | commitdiff | raw | diff to current |
| 2014-12-01 | Andrew Waterman | Implement timer faithfully | blob | commitdiff | raw | diff to current |
| 2014-04-03 | Stephen Twigg | Merge branch 'tm' | blob | commitdiff | raw | diff to current |
| 2014-03-18 | Andrew Waterman | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH | blob | commitdiff | raw | diff to current |
| 2014-01-21 | Quan Nguyen | Merge branch 'confprec' | blob | commitdiff | raw | diff to current |
| 2013-12-09 | Andrew Waterman | New RDCYCLE encoding | blob | commitdiff | raw | diff to current |
| 2013-11-25 | Andrew Waterman | Update to new privileged ISA | blob | commitdiff | raw | diff to current |