Support setting ISA/subsets with --isa flag
[riscv-isa-sim.git] / riscv / sim.cc
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2014-08-15 Christopher CelioAdded PC histogram option.
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-29 Andrew WatermanPass target machine's return code back to OS
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-09-23 Andrew WatermanFix Scott's deadlock
2013-09-11 Andrew WatermanImplement zany immediates
2013-09-10 Andrew WatermanDon't tick HTIF as often
2013-08-13 Andrew WatermanImplement RoCC and add a dummy RoCC
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-22 Andrew WatermanAdd xspike program
2013-07-20 Andrew WatermanUse calloc to allocate target memory
2013-07-13 Andrew WatermanEliminate infinite loop in debug mode
2013-07-13 Andrew WatermanExit cleanly from debug console
2013-07-13 Andrew WatermanFavor procs.size() over num_cores()
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermanadd missing #include
2013-02-13 Andrew Watermanmake HTIF interactions deterministic; fix race
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-05-16 Andrew Watermanfix htif interaction with interactive mode
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-02-09 Yunsup Leeinitialize tohost and fromhost
2012-02-01 Andrew Watermanpoll HTIF occasionally
2011-11-11 Andrew WatermanChanged supervisor mode
2011-10-19 Yunsup LeeMerge branch 'master' of github.com:ucb-bar/riscv-isa-sim
2011-10-19 Yunsup Leeyunsup made this fix..ask him
2011-06-27 Andrew WatermanBuilds and runs on Mac OS 10.6.7
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2010-12-27 Andrew Waterman[sim] fixed some compiler warnings
2010-11-22 Andrew Waterman[xcc, sim, pk] link register is now x1
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-08 Yunsup Lee[sim] change applink for tohost/fromhost
2010-09-07 Andrew Waterman[sim] fixed bug in msub.d; added ability to print FPRs...
2010-08-10 Andrew Waterman[sim] removed unused elf loader
2010-07-23 Yunsup Lee[sim] various fixes to get the sim work with the fesvr
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure