add BSD license
[riscv-isa-sim.git] / riscv / sim.h
2013-03-26 Andrew Watermanadd BSD license
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-05-16 Andrew Watermanfix htif interaction with interactive mode
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-07 Andrew Waterman[sim] fixed bug in msub.d; added ability to print FPRs...
2010-08-10 Andrew Waterman[sim] removed unused elf loader
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure