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try setting domain to "CPU"
[libresoc-litex.git]
/
libresoc
/
core.py
2021-06-09
Luke Kenneth Casso...
try setting domain to "CPU"
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2021-06-09
Luke Kenneth Casso...
add PLL clock loop-back into CPU
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2021-06-09
Luke Kenneth Casso...
add PLL clock loop-back into CPU
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2021-06-03
Luke Kenneth Casso...
dummy PLL added with bypass, rename ref to ref_v due...
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2021-05-26
Luke Kenneth Casso...
remove wb err signal from sram4k
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2021-05-22
Luke Kenneth Casso...
match up PLL names
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2021-05-22
Luke Kenneth Casso...
match up PLL names
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2021-05-22
Luke Kenneth Casso...
rename vco_test_ana to pll_testout_o
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2021-05-09
Luke Kenneth Casso...
code-comments about ls180 imports
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2021-04-18
Luke Kenneth Casso...
sort out names
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2021-04-18
Luke Kenneth Casso...
whoops clk_sel_i renamed accidentally
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2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
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2021-04-18
Luke Kenneth Casso...
add SPBlock_512W64B8W.v to sources
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2021-04-18
Luke Kenneth Casso...
put imports into conditional blocks. makes core.py...
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2021-04-08
Luke Kenneth Casso...
reduce jtag data bus width to 32, to match litex
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2021-04-05
Luke Kenneth Casso...
sort out sdr and sdmmc OE pad drive, no longer one...
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2021-04-01
Luke Kenneth Casso...
disable PLL for litex build, new variant
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2021-03-28
Luke Kenneth Casso...
fix issues with port direction on several pads
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2021-03-27
Luke Kenneth Casso...
latest fighting with litex to get pad directions connec...
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2021-03-25
Luke Kenneth Casso...
debugging ls180 litex hell
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2021-03-22
Luke Kenneth Casso...
sort out naming of IOpads for bi-directional pins
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2021-03-12
Luke Kenneth Casso...
splitting out litex files from soc repo into separate...
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