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[riscv-isa-sim.git] / riscv / encoding.h
2019-06-27 Luke Kenneth Casso... rename SV CSRs, to use CSR_UESVSTATE etc.
2019-06-27 Luke Kenneth Casso... add subvl to headers, comment out state-cfg
2018-11-13 Luke Kenneth Casso... redo SV CSRs to use a stack-based mechanism
2018-11-03 Luke Kenneth Casso... add remap and shape sv csrs
2018-10-16 Luke Kenneth Casso... shuffle CSR offsets around, offset VL and MVL by one
2018-10-05 Luke Kenneth Casso... add srcoffs and destoffs sv state, alter CSRs
2018-09-29 Luke Kenneth Casso... a LOT of debugging and fixing, sv loop actually working
2018-09-29 Luke Kenneth Casso... move SV CSRs to user-read-write
2018-09-29 Luke Kenneth Casso... add 8 CSRs for registers and predication each
2018-09-29 Luke Kenneth Casso... whoops dont need separate SVSETVL/SVGETVL CSRs
2018-09-29 Luke Kenneth Casso... revert addition of svsetvl as an actual opcode, add...
2018-09-29 Luke Kenneth Casso... Revert "sv setvl as a csr not going to work, add getvl...
2018-09-29 Luke Kenneth Casso... Revert "manually add svsetvl instruction"
2018-09-28 Luke Kenneth Casso... manually add svsetvl instruction
2018-09-28 Luke Kenneth Casso... sv setvl as a csr not going to work, add getvl only
2018-09-27 Luke Kenneth Casso... adding sv vector length CSR to processor state, and...
2017-11-27 Andrew WatermanRename badaddr to tval
2017-11-27 Andrew WatermanRename sptbr to satp
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-05-05 Andrew WatermanUXL=SXL=MXL
2017-04-25 Andrew WatermanFMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
2017-04-25 Andrew WatermanRemove hret instruction
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-01 Yunsup Leeupdate encoding.h to get PMP updates
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2017-03-23 Andrew WatermanRequire little-endian host
2017-03-22 Wesley W. Terpstrariscv: replace rtc device with a real clint implementation
2017-03-21 Wesley W. Terpstrariscv: remove dependency on num_cores
2017-03-20 Andrew WatermanPUM -> SUM; expose MXR to S-mode
2017-03-16 Andrew WatermanSimplify interrupt-stack discipline
2017-03-13 Andrew WatermanImplement mstatus.TW, mstatus.TVM, and mstatus.TSR
2017-02-27 Andrew WatermanSv57 and Sv64 are not spec'd yet
2017-02-25 Andrew WatermanNew counter enable scheme
2017-02-18 Andrew WatermanSpike uarch needs TLB flush after SPTBR write
2017-02-15 Andrew Watermansfence.vm -> sfence.vma
2017-02-08 Andrew WatermanEncode VM type in sptbr, not mstatus
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-08-29 Tim NewsomeRename tdata0--tdata2 to tdata1--tdata3.
2016-08-27 Andrew WatermanAdd (degenerate) performance counter facility
2016-08-26 Andrew Watermanpartially update spike to newer debug spec
2016-08-22 Tim NewsomeImplement address and data triggers.
2016-07-06 Andrew WatermanUpdate to new PTE format
2016-06-18 Andrew WatermanMerge sasid into sptbr
2016-06-09 Andrew WatermanAdd degenerate HW breakpoint implementation
2016-06-03 Tim NewsomeKeep DCSR_XDEBUGVER unsigned.
2016-05-24 Tim NewsomeNew encoding.h for new CSR addresses.
2016-05-23 Tim NewsomeChange DCSR bits to match spec.
2016-05-23 Tim NewsomeRemove dependency on include file in my homedir.
2016-05-23 Tim NewsomeSoftware breakpoints sort of work.
2016-05-23 Tim NewsomeRemove unused code.
2016-05-23 Tim NewsomeAdd dret.
2016-05-22 Andrew WatermanAllow delegation of device interrupts
2016-05-02 Andrew WatermanRemove MIPI; mip.MSIP bit is read-only
2016-05-01 Andrew WatermanRemove SCRs; add padding after config string
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-04-20 Andrew WatermanSplit ERET into URET, SRET, HRET, MRET
2016-04-06 Andrew WatermanRemove non-standard uarch CSRs
2016-03-04 Andrew WatermanFix up interrupt delegation
2016-03-02 Andrew WatermanAdd counter-enable registers
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanNew definitions of misa/marchid/mvendorid
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew WatermanUse simpler MTVEC scheme
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-20 Andrew WatermanUpdate to hopefully final RVC 1.9 encoding
2015-10-06 Andrew WatermanRVC encoding tweak
2015-10-06 Andrew Watermanmore work towards RVC 1.8
2015-10-02 Andrew Watermanwork towards rvc 1.8
2015-09-09 Andrew WatermanImprove instruction fetch
2015-09-04 Andrew WatermanMove towards RVC v1.8
2015-09-02 Andrew WatermanDon't automatically run autoconf
2015-07-05 Andrew WatermanNew machine-mode timer facility
2015-06-01 Andrew WatermanAdd rest of RV32C instructions
2015-06-01 Andrew WatermanNew RV64C proposal
2015-05-15 Andrew WatermanMerge pull request #20 from palmer-dabbelt/package
2015-05-14 Andrew WatermanFix VM, MIP encoding
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-31 Andrew WatermanImplement RVC draft
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-13 Andrew WatermanUse hcall instead of mcall
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2014-11-22 Yunsup LeeRevert "Enable support for the four custom instructions"
2014-10-24 Yunsup LeeMerge pull request #4 from arunthomas/custom_inst
2014-10-23 Arun ThomasEnable support for the four custom instructions
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-04-03 Stephen TwiggSync encoding in opcodes
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-12 Andrew WatermanNew FP encoding
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-15 Andrew WatermanRenumber uarch CSRs into custom CSR space
2014-02-06 Yunsup Leecommit missing definitions for uarch counters
2014-01-22 Andrew WatermanUse auto-generated trap cause numbers
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
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