| 2021-05-26 |
Luke Kenneth Casson... | add ldst PortInterface misalign unit test (underway)
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commit | commitdiff | tree |
| 2021-05-26 |
Luke Kenneth Casson... | rename PLL signals
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commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | whoops sort out name of SPBlock RAM
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commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | change name of submodule to real_pll
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commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | match up PLL names
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commit | commitdiff | tree |
| 2021-05-22 |
Luke Kenneth Casson... | update submodule
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commit | commitdiff | tree |
| 2021-05-22 |
Luke Kenneth Casson... | update PLL to use Instance
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commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | add radix MMU "miss" test
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commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | clear out request data on return to idle
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commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | sort out LoadStore1 misalignment FSM, also required...
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commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | remove minerva units previously missed in cleanout
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commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | add misaligned load through MMU (which is incorrectly...
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | minor rework of wb_get, make generic
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | added STORE test in test_ldst_pi.py, and it worked...
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | update comments in issuer.py regarding a 4th FSM
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | yet more debug log stuff for DCache, this time on CacheRam...
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | fix wb_get error where data was being corrupted
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | add read at different locations in test_ldst_pi.py
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | add some data for MMU to actually look up
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | ha, hilarious: swapped TLBUpdate output sizes db_out...
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | whoops TLBIE must *clear* the valid bit not set it...
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | more debug Display in dcache.py
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commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | putting in a lot more debug print statements in DCache...
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | add dcache tlb / pte test
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | set m_out.load from ldst_r(egister) in LoadStore1
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | move dcache unit test to separate test_dcache.py
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | experimentation with MMU-enabled LoadStore1 through...
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | add debug info, update comments, disable dcache in...
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | start doing virtual memory queries via PortInterface...
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whoops missing default zero (no idea how)
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | addcomments for MMU PortInterface test (how it, um...
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | bit of a hack to get test_mmu_dcache_pi.py operational.
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | no need for sel0
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | pass through MSR.PR through PortInterface, into LoadStore1
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | connect MSR.PR to PortInterface in LDSTCompUnit
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add msr_pr bit in PortInterface
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add MSR to LD/ST Input Record
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | comment tidyup
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | must also pass through instruction fault exception...
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | whoops names changed in MMU FSM
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | tidyup comments and remove LoadStore COMPLETE state
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | cleanup on exception setting
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commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | rename LoadStore1 data structures back to microwatt...
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commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add block for MMU activation to LoadStore1
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commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
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commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | whoops, indentation issue on m.If/m.Else in dcache.py
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commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add links to set associative image, and bugreport
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments on translation of MMU_LOOKUP
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | install MMU_LOOKUP vhdl to be translated to nmigen
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | move (unused) ACK_WAIT code into FSM
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments in LoadStore1
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove invalid setting of d_in.valid from self.mmureq
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | no SECOND_REQ
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove SECOND_REQ
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comment about LD/ST exception needs copying into...
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | run LD/ST Exception test case for MMU
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add MMU bugtracker link
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | git submodule update
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | update code-comments
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add in alignment exception capture/reporting in LoadStore1
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | preference is to create a temp variable for comb and...
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commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add misalign flag to PortInterfaceBase
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commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | LoadStore1 tidyup
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commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | transferring more over to LoadStore FSM
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commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | start putting state info into LoadStore1, slowly putting...
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commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add LoadStore State enum
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commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add bugreport link to mmu
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | start setting DSISR bits but commented out
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | update comments and docstrings
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops, import error
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move LoadStore1 class to soc.fu.ldst.loadstore
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops was still copying output over in CommonOutputStage
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | how we managed to get this far without noticing that...
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move dsisr and dar into LoadStore1
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move zero-dest-pred in Common Output Stage to not copy...
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commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops setup of core.sv_pred_sm/dm not indented and...
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | whoops disabled tests agaaaaain
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass relevant predicate mask bits through to Decoders...
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | add in predicate mask bit detection when zeroing is...
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass SVP64 ReMap field through to core and then on...
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | moved exts* SVP64 unit tests to a different location
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | argh someobe falsely stated in the README that LibreSOC...
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commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | if zeroing is set, put zero into input or output as...
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | simplify README.md so that it gets submitted to pypi
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | mark long description type as markdown
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | update NEWS.txt
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add libresoc-openpower-isa to setup.py dependencies
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | put sv_input_record_layout onto CompOpSubsetBase after all
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | whoops wrong signal name, set exc_happened
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commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add SVP64 RM fields to ALU input record
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commit | commitdiff | tree |
| 2021-05-04 |
Luke Kenneth Casson... | remove minerva debug unit (not needed)
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | minerva tests: Don't import soc.minerva.csr
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Silence pywriter harder
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Trim log output
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Fix invocation of pywriter
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build power-instruction-analyzer
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build c4m-jtag
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build openpower-isa
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commit | commitdiff | tree |
| 2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Install Rust and cargo
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