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rather invasive reduction of SPR regfile size
2021-03-28 Luke Kenneth Casson... rather invasive reduction of SPR regfile size
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2021-03-28 Luke Kenneth Casson... add option to reduce number of regfile ports (get DFFs...
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2021-03-28 Luke Kenneth Casson... reduce number of regfile ports
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2021-03-28 Luke Kenneth Casson... reduce regfile port usage on non-svp64
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2021-03-24 Luke Kenneth Casson... comment about using PriorityEncoder
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2021-03-24 Luke Kenneth Casson... debug output
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2021-03-24 Luke Kenneth Casson... add comment skipping in pagereader.py
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2021-03-24 Luke Kenneth Casson... make svp64 isa caller unit tests more obvious
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2021-03-24 Luke Kenneth Casson... add option to stop writing isa all.py in pseudocode...
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2021-03-24 Luke Kenneth Casson... fix nonzero test in ISACaller RADIXMMU
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2021-03-24 Luke Kenneth Casson... add --disable-svp64 to litex sim build
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2021-03-22 Luke Kenneth Casson... do not set sv_changed
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2021-03-22 Luke Kenneth Casson... read predicate mask from correct point in SVP64Asm
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2021-03-22 Luke Kenneth Casson... add SVP64Asm option for "m=" to set both src and dest...
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2021-03-22 Luke Kenneth Casson... add very small dff sram variant (no 4k SRAMs)
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2021-03-22 Luke Kenneth Casson... make sure non-svp64-mode works
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2021-03-22 Luke Kenneth Casson... have get_predint return indicator that mask is all 1s
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2021-03-21 Luke Kenneth Casson... more TODO comments
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2021-03-21 Luke Kenneth Casson... add for-loop pseudocode for CR predicate mask reading
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2021-03-21 Luke Kenneth Casson... code comments in TestIssuer
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2021-03-21 Luke Kenneth Casson... adjust syntax of SVP64 predicate test cas
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2021-03-21 Luke Kenneth Casson... naah. back to "sv." syntax for SVP64 assembly
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2021-03-21 Luke Kenneth Casson... add override for build commands powerpc64-linux-gnu...
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2021-03-21 Luke Kenneth Casson... enable -mregnames in assembly syntax for unit tests
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2021-03-20 Luke Kenneth Casson... more pseudocode in TestIssuer
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2021-03-20 Luke Kenneth Casson... move radixmmu to unit test format
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2021-03-20 Luke Kenneth Casson... add harmless code and commented-out pseudocode for...
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2021-03-20 Luke Kenneth Casson... sort out predicate zeroing in ISACaller
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2021-03-20 Luke Kenneth Casson... attempting to add src/dest-zeroing to ISACaller
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2021-03-19 Luke Kenneth Casson... more comments for TestIssuer when adding predication
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2021-03-19 Luke Kenneth Casson... decode predicate src/dest zeroing in SVP64RMModeDecode
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2021-03-19 Luke Kenneth Casson... comments for TestIssuer get_predint and get_predcr
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2021-03-19 Luke Kenneth Casson... add more pieces of predication reading puzzle to TestIssuer
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2021-03-19 Luke Kenneth Casson... cleanup TestIssuer (comments)
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2021-03-19 Luke Kenneth Casson... spelling
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2021-03-19 Luke Kenneth Casson... code-shuffle in TestIssuer, split out setting up peripherals
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2021-03-19 Luke Kenneth Casson... move duplicated code to a function in TestIssuer
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2021-03-18 Luke Kenneth Casson... more hint/comments
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2021-03-18 Luke Kenneth Casson... comments / code-shuffle
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2021-03-18 Luke Kenneth Casson... update TestIssuer comments
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2021-03-18 Luke Kenneth Casson... add comments on most likely place to put predicate...
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2021-03-18 Luke Kenneth Casson... comments TestIssuer, add a stub FSM
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2021-03-18 Luke Kenneth Casson... add MSR PR read in RADIXMMU ISACaller
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2021-03-18 Luke Kenneth Casson... re-add auto-generated file simplev.py to gitignore
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2021-03-18 Luke Kenneth Casson... experiment in radixmmu with returning addr_next (and...
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2021-03-18 Luke Kenneth Casson... add sv_out2 to PowerDecode and PowerDecoder2
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2021-03-18 Luke Kenneth Casson... cross-reference to bug #619
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2021-03-18 Luke Kenneth Casson... add auto-generation of out2 column in SVP64RM
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2021-03-18 Luke Kenneth Casson... remove nmigen-type-annotations temporarily
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2021-03-18 Luke Kenneth Casson... remove nmigen-type-annotations temporarily
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2021-03-18 Luke Kenneth Casson... add option to move RS in CSV file reading, for compatibility...
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2021-03-17 Luke Kenneth Casson... correct comments
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2021-03-17 Luke Kenneth Casson... re-enable SVP64 ISACaller predicate tests
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2021-03-17 Luke Kenneth Casson... add ascii graphic for extsw svp64 operation
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2021-03-17 Luke Kenneth Casson... add more explanatory comments
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2021-03-17 Luke Kenneth Casson... add twin-predicated extsw SVP64 ISACaller unit test
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2021-03-17 Luke Kenneth Casson... add SVP64 dststep incrementing in PowerDecoder2, Testissuer...
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2021-03-17 Luke Kenneth Casson... add CR-based predication to ISACaller
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2021-03-17 Luke Kenneth Casson... add SVP64 INT-style predication to ISACaller
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2021-03-17 Luke Kenneth Casson... add predication SVP64 unit test
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2021-03-17 Luke Kenneth Casson... add predication read ports (CR and INT)
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2021-03-17 Luke Kenneth Casson... whoops shift has to be done at same bitwidth
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2021-03-17 Luke Kenneth Casson... split out new_lookup function
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2021-03-17 Luke Kenneth Casson... link up SVP64 RM Mode decoding into PowerDecoder2
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2021-03-17 Luke Kenneth Casson... add priv and mode to RADIXMMU
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2021-03-17 Luke Kenneth Casson... add instr_fetch mode to ISACaller Mem and RADIXMMU
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2021-03-17 Luke Kenneth Casson... whitespace
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2021-03-17 Luke Kenneth Casson... add in SVP64 RM Mode decoder
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2021-03-14 Luke Kenneth Casson... remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14 Luke Kenneth Casson... remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-13 Luke Kenneth Casson... add setvl unit test assertions, add 2nd test
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2021-03-13 Luke Kenneth Casson... get first revision setvl operational in ISACaller
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2021-03-13 Luke Kenneth Casson... add setvl-to-long converter in SVP64Asm (sigh)
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2021-03-13 Luke Kenneth Casson... add setvl unit test
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2021-03-13 Luke Kenneth Casson... update submodule to include simplev setvl
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2021-03-13 Luke Kenneth Casson... include SVSTATE in namespace, passing to ISACaller
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2021-03-12 Luke Kenneth Casson... add OP_SETVL to MicrOp in power_enums.py
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2021-03-12 Luke Kenneth Casson... add ability to set and distinguish RT=0 (RT_OR_ZERO...
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2021-03-12 Luke Kenneth Casson... use PowerDecoder2.loop_continue instead of no_out_vec
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2021-03-12 Luke Kenneth Casson... remove old code
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2021-03-12 Luke Kenneth Casson... remove old code
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2021-03-12 Luke Kenneth Casson... remove old code
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2021-03-12 Luke Kenneth Casson... add more sophisticated checking of whether SVP64 loop...
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2021-03-12 Luke Kenneth Casson... **FOR NOW** LD/ST relies on detection of twin-predication...
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2021-03-12 Luke Kenneth Casson... decoding of svp64 reg by name has to occur after immediate...
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2021-03-11 Luke Kenneth Casson... add link of RA_OR_ZERO SVP64 detection
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2021-03-11 Luke Kenneth Casson... add detection of whether *full* 7-bit of RA is zero...
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2021-03-11 Luke Kenneth Casson... add in SVP64 LD/ST basic test for ISACaller
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2021-03-11 Luke Kenneth Casson... whoops sort out when svstate not active in ISACaller
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2021-03-11 Luke Kenneth Casson... whoops PIDR is defined as 32-bits in SPRs.csv (and...
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2021-03-11 Luke Kenneth Casson... add understanding of LDST immediates to SVP64ASM
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2021-03-10 Luke Kenneth Casson... add walk_tree arguments it needs
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2021-03-09 Luke Kenneth Casson... fix address must convert to SelectableInt
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2021-03-09 Luke Kenneth Casson... call decode_ptre on address to obtain shift, mbits...
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2021-03-09 Luke Kenneth Casson... debug radix mmu ISACaller
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2021-03-09 Luke Kenneth Casson... create first check_perms RADIX ISACaller function
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2021-03-09 Luke Kenneth Casson... move Mem class out of ISACaller
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2021-03-09 Luke Kenneth Casson... cleanup imports
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2021-03-09 Luke Kenneth Casson... move ISACaller RADIX MMU class to separate module
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2021-03-09 Luke Kenneth Casson... add pgtable and pte calculation to RADIX ISACaller
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