jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO));
memset(debug_abstract, 0, sizeof(debug_abstract));
-
+
}
void debug_module_t::reset()
memcpy(bytes, dmdata + addr - debug_data_start, len);
return true;
}
-
+
if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
memcpy(bytes, program_buffer + addr - debug_progbuf_start, len);
return true;
}
addr = DEBUG_START + addr;
-
+
if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) {
memcpy(dmdata + addr - debug_data_start, bytes, len);
return true;
}
-
+
if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + sizeof(program_buffer)))) {
fprintf(stderr, "Successful write to program buffer %d bytes at %x\n", (int) len, (int) addr);
memcpy(program_buffer + addr - debug_progbuf_start, bytes, len);
-
+
return true;
}
} else {
dmstatus.allresumeack = false;
}
-
+
result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
//NOP
write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
}
-
+
if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
// Since the next instruction is what we will use, just use nother NOP
// to get there.
}
debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
-
+
abstractcs.busy = true;
} else {
abstractcs.cmderr = CMDERR_NOTSUP;
} else if (address >= DMI_PROGBUF0 && address < DMI_PROGBUF0 + progsize) {
unsigned i = address - DMI_PROGBUF0;
-
+
if (!abstractcs.busy)
write32(program_buffer, i, value);
perform_abstract_command();
}
return true;
-
+
} else {
switch (address) {
case DMI_DMCONTROL:
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc = debug_rom_entry();
+ state.pc = DEBUG_ROM_ENTRY;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
- state.pc = debug_rom_entry();
+ state.pc = DEBUG_ROM_ENTRY;
} else {
state.pc = DEBUG_ROM_TVEC;
}
bool slow_path();
bool halted() { return state.dcsr.cause ? true : false; }
bool halt_request;
- // The unique debug rom address that this hart jumps to when entering debug
- // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
- uint32_t debug_rom_entry() {
- fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id);
- return DEBUG_ROM_ENTRY + 4 * id;
- }
// Return the index of a trigger that matched, or -1.
inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)