Implement autoexec. DMI op 2 is just write now.
[riscv-isa-sim.git] / debug_rom /
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-09-02 Tim NewsomeRebuild debug ROM because CSR encoding changed.
2016-06-23 Andrew WatermanParameterize debug ROM contents on XLEN
2016-06-23 Andrew WatermanRemove fence.i from debug ROM
2016-06-09 Tim NewsomeFix 2 bugs in Debug ROM: (#52)
2016-06-03 Tim NewsomeDCSR cause was moved, bug debug ROM wasn't updated
2016-06-01 Andrew WatermanAdd gitignore
2016-06-01 Tim NewsomeMove sethaltnot and cleardebint.
2016-05-24 Tim NewsomeNew encoding.h for new CSR addresses.
2016-05-24 Tim NewsomeMove cleardebint, per spec.
2016-05-23 Tim NewsomeChange DCSR bits to match spec.
2016-05-23 Tim NewsomeMove debug rom link map to the right place.
2016-05-23 Tim NewsomeUse fence.i in Debug ROM.
2016-05-23 Tim NewsomeAdd dret.
2016-05-23 Tim NewsomeImplement single memory read access.
2016-05-23 Tim NewsomeExceptions in Debug Mode, stay in Debug Mode.
2016-05-23 Tim NewsomeHave Debug memory kind of working again.
2016-05-23 Tim NewsomeFix race using fence.
2016-05-23 Tim NewsomeRefactor how we track in-progress operations.
2016-05-23 Tim Newsomeprocessor_t unfriends gdbserver_t.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeROM -> RAM -> ROM, waiting for debug int.
2016-05-23 Tim NewsomeJump to the correct (temporary) Debug RAM address.
2016-05-23 Tim NewsomeClean up how Debug ROM is included.
2016-05-23 Tim NewsomeCan jump to and execute Debug ROM.
2016-05-23 Tim NewsomeCheck in compiled debug ROM.
2016-05-23 Tim NewsomeAdd debug rom code.