| 2019-06-28 |
Luke Kenneth Casso... | remove ssvoffs from SVSTATE |
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| 2019-06-28 |
Luke Kenneth Casso... | mess with CSR_SV_STATE set |
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| 2019-06-28 |
Luke Kenneth Casso... | printf wrong args |
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| 2019-06-28 |
Luke Kenneth Casso... | vl, mvl, subvl should all be 1 when returned from CSR_S... |
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| 2019-06-27 |
Luke Kenneth Casso... | add sesvstate / mesvstate, set on entry to trap |
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| 2019-06-27 |
Luke Kenneth Casso... | rename SV CSRs, to use CSR_UESVSTATE etc. |
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| 2019-06-27 |
Luke Kenneth Casso... | make vlen loop run times subvl, set subvl default to... |
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| 2019-06-27 |
Luke Kenneth Casso... | initialise SUBVL to 1 |
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| 2019-06-27 |
Luke Kenneth Casso... | add get on subvl |
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| 2019-06-27 |
Luke Kenneth Casso... | alter STATE CSR to support subvl |
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| 2019-06-27 |
Luke Kenneth Casso... | add SUBVL CSR set |
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| 2019-06-27 |
Luke Kenneth Casso... | add SUBVL CSR set |
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| 2019-06-27 |
Luke Kenneth Casso... | add subvl to headers, comment out state-cfg |
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| 2019-06-27 |
Luke Kenneth Casso... | rename packed field to fail-on-first |
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| 2018-11-15 |
Luke Kenneth Casso... | add predication remap option |
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| 2018-11-13 |
Luke Kenneth Casso... | change SV_REGCSR csrrwi to different meaning: 5-bit... |
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| 2018-11-13 |
Luke Kenneth Casso... | modify csrrwi and csrrw back to original, change old... |
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| 2018-11-13 |
Luke Kenneth Casso... | whoops missing brackets |
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| 2018-11-13 |
Luke Kenneth Casso... | alter set_csr to call get_csr, will make csrrw* easier |
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| 2018-11-13 |
Luke Kenneth Casso... | redo SV CSRs to use a stack-based mechanism |
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| 2018-11-05 |
Luke Kenneth Casso... | add CSR_USVCFG set/get |
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| 2018-11-05 |
Luke Kenneth Casso... | correct bank and size, use in setting up CSR tables |
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| 2018-11-05 |
Luke Kenneth Casso... | move csr reg and predicate table unpack to separate... |
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| 2018-11-05 |
Luke Kenneth Casso... | add state and bank sv csr bitfields |
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| 2018-11-04 |
Luke Kenneth Casso... | debug shape remap |
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| 2018-11-03 |
Luke Kenneth Casso... | raise exception if permutation set to reserved value |
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| 2018-11-03 |
Luke Kenneth Casso... | add reshaping algorithm for elements |
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| 2018-11-03 |
Luke Kenneth Casso... | add sv shape CSRs |
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| 2018-11-03 |
Luke Kenneth Casso... | add placeholder CSR uremap get |
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| 2018-11-03 |
Luke Kenneth Casso... | add remap CSR set |
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| 2018-11-03 |
Luke Kenneth Casso... | add reshape data structures and get_shape function |
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| 2018-11-03 |
Luke Kenneth Casso... | add state redirection for CSR get/set depending on... |
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| 2018-10-25 |
Luke Kenneth Casso... | add variable bitwidth on read/write regs |
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| 2018-10-18 |
Luke Kenneth Casso... | put sv_mmu override class in place |
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| 2018-10-18 |
Luke Kenneth Casso... | use unsigned long shift on sv csr setting |
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| 2018-10-18 |
Luke Kenneth Casso... | forgot to set clroffset |
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| 2018-10-17 |
Luke Kenneth Casso... | allow 4 CSR entries to be set at a time, on RV64 |
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| 2018-10-17 |
Luke Kenneth Casso... | minor alteration to CSRRWI SETVL / SETMVL to offset... |
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| 2018-10-16 |
Luke Kenneth Casso... | shuffle CSR offsets around, offset VL and MVL by one |
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| 2018-10-13 |
Luke Kenneth Casso... | rename _zext_xlen |
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| 2018-10-12 |
Luke Kenneth Casso... | combination of redirection through a "property" class... |
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| 2018-10-11 |
Luke Kenneth Casso... | redirect instructions through a class called sv_proc_t |
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| 2018-10-09 |
Luke Kenneth Casso... | extend sv register file from 64 to 128 after discussion. |
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| 2018-10-05 |
Luke Kenneth Casso... | add srcoffs and destoffs sv state, alter CSRs |
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| 2018-09-30 |
Luke Kenneth Casso... | lots of debugging of predication, found other errors |
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| 2018-09-29 |
Luke Kenneth Casso... | a LOT of debugging and fixing, sv loop actually working |
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| 2018-09-29 |
Luke Kenneth Casso... | add near-duplicate of SV CFG REG CSRs, for predication |
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| 2018-09-29 |
Luke Kenneth Casso... | add implementation of CSR SV CFG regs 0-7 |
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| 2018-09-29 |
Luke Kenneth Casso... | assign SV REG CSRs (using new union ability) |
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| 2018-09-29 |
Luke Kenneth Casso... | fix bug in CSR set SVVL: val has already been looked up |
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| 2018-09-29 |
Luke Kenneth Casso... | add stub for SV REG configs |
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| 2018-09-29 |
Luke Kenneth Casso... | whoops dont need separate SVSETVL/SVGETVL CSRs |
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| 2018-09-29 |
Luke Kenneth Casso... | revert addition of svsetvl as an actual opcode, add... |
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| 2018-09-29 |
Luke Kenneth Casso... | Revert "sv setvl as a csr not going to work, add getvl... |
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| 2018-09-28 |
Luke Kenneth Casso... | sv setvl as a csr not going to work, add getvl only |
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| 2018-09-27 |
Luke Kenneth Casso... | adding sv vector length CSR to processor state, and... |
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| 2018-08-22 |
Andrew Waterman | Make IRQ_COP read-only/undelegable unless coprocessor... |
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| 2018-08-21 |
Andrew Waterman | Instantiate disassembler after max_xlen is known |
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| 2018-08-18 |
Andrew Waterman | Don't increment instret immediately after it is written... |
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| 2018-07-31 |
Andrew Waterman | Make sstatus.MXR readable |
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| 2018-07-23 |
SeungRyeol Lee | Fix using the uninitialized disassemble object. (#220) |
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| 2018-07-10 |
Andrew Waterman | Refactor and fix LR/SC implementation (#217) |
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| 2018-05-31 |
Andy Wright | Put simif_t declaration in its own file. (#209) |
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| 2018-03-22 |
Andrew Waterman | Implement Hauser misa.C misalignment proposal (#187) |
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| 2018-03-19 |
Tim Newsome | Fix spike-dasm. (#184) |
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| 2018-03-19 |
Tim Newsome | Merge pull request #182 from riscv/reset_bits |
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| 2018-03-16 |
Tim Newsome | Implement debug havereset bits |
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| 2018-03-16 |
Andrew Waterman | Merge branch 'deepsrc-b_fix_issue183' |
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| 2018-03-14 |
Prashanth Mundkur | Fix a bug caused by moving misa into state_t. (#180) |
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| 2018-03-13 |
Prashanth Mundkur | Move processor.isa to state.misa, since it really belon... |
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| 2018-03-08 |
Tim Newsome | Merge pull request #177 from riscv/debug_auth |
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| 2018-03-06 |
Prashanth Mundkur | Narrow the interface used by the processors and memory... |
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| 2018-03-03 |
Andrew Waterman | Enforce 2-byte alignment of mepc/sepc/dpc |
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| 2018-02-19 |
Tim Newsome | Merge pull request #171 from riscv/sysbusbits |
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| 2018-02-13 |
Andrew Waterman | Implement cycleh/instreth CSRs for RV32 (#172) |
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| 2017-11-27 |
Andrew Waterman | Rename badaddr to tval |
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| 2017-11-27 |
Andrew Waterman | Rename sptbr to satp |
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| 2017-11-27 |
Andrew Waterman | Set tval to 0 on traps with no specified tval |
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| 2017-11-20 |
Andrew Waterman | Implement priv-1.11 interrupt-priority scheme (#161) |
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| 2017-11-16 |
Andrew Waterman | Merge pull request #156 from p12nGH/noncontiguous_harts |
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| 2017-11-10 |
Andrew Waterman | Remove redundant U/S mode advertisement |
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| 2017-11-10 |
Andrew Waterman | H-mode no longer exists |
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| 2017-11-10 |
Andrew Waterman | MPP is now WARL |
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| 2017-11-03 |
Andrew Waterman | Mask medeleg correctly |
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| 2017-11-02 |
Andrew Waterman | Don't permit delegation of interrupts that M-mode shoul... |
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| 2017-10-11 |
Andrew Waterman | Merge pull request #129 from riscv/q-extension |
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| 2017-09-28 |
Andrew Waterman | Implement Q extension |
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| 2017-09-21 |
Tim Newsome | Fix corner case in repeated execution (#127) |
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| 2017-09-12 |
Tim Newsome | Merge pull request #123 from riscv/debug_interrupts |
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| 2017-09-12 |
Tim Newsome | Don't take interrupts while in Debug Mode. |
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| 2017-08-10 |
Tim Newsome | Merge pull request #117 from riscv/multicore_debug |
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| 2017-08-07 |
Tim Newsome | Fix multicore debug. |
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| 2017-05-17 |
Palmer Dabbelt | Merge remote-tracking branch 'origin/priv-1.10' |
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| 2017-05-16 |
Palmer Dabbelt | Merge remote-tracking branch 'origin/debug-0.13' into... |
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| 2017-05-15 |
Megan Wachs | Merge branch 'debug-0.13' into HEAD |
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| 2017-05-05 |
Andrew Waterman | UXL=SXL=MXL |
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| 2017-04-26 |
Palmer Dabbelt | Merge pull request #96 from riscv/ndmreset |
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| 2017-04-26 |
Palmer Dabbelt | Remove a debugging printf |
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| 2017-04-18 |
Megan Wachs | debug: Checkpoint which somewhat works with OpenOCD... |
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| 2017-04-18 |
Megan Wachs | debug: Move things around, but addresses now conflict... |
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