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2022-04-17	Cesar Strauss	Add transparent option for the full read port	commit \| commitdiff \| tree
2022-04-17	Cesar Strauss	Implement a pseudo 1W/2R memory	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Check non-transparent 1W/1R SRAM wrapper	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Enable read port for non-transparent memories	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Add port declarations to the SRAM wrappers	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Change write lane signal from one-hot to binary	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Synchronize LVT state, completing the induction proof	commit \| commitdiff \| tree
2022-04-16	Cesar Strauss	Sync proof state with downstream memories	commit \| commitdiff \| tree
2022-04-15	Cesar Strauss	Complete moving the induction support into the DUT	commit \| commitdiff \| tree
2022-04-15	Cesar Strauss	Fix incorrect signal widths	commit \| commitdiff \| tree
2022-04-15	Cesar Strauss	Move part of formal proof to the implementation	commit \| commitdiff \| tree
2022-04-10	Cesar Strauss	Begin a formal proof of the LVT-based 1W/1R wrapper	commit \| commitdiff \| tree
2022-04-10	Cesar Strauss	Implement 1W/1R with a transparent (or not) read port.	commit \| commitdiff \| tree
2022-04-10	Cesar Strauss	Implement a true 1W/1R memory from 1RW blocks	commit \| commitdiff \| tree
2022-04-03	Cesar Strauss	Extend the proof to a non-transparent port	commit \| commitdiff \| tree
2022-04-03	Cesar Strauss	Run formal proof on both types (even/odd) of phased...	commit \| commitdiff \| tree
2022-04-03	Cesar Strauss	Complete the formal proof of the pseudo dual port SRAM	commit \| commitdiff \| tree
2022-04-03	Cesar Strauss	Implement a debug port on the pseudo 1W/1R SRAM	commit \| commitdiff \| tree
2022-04-03	Cesar Strauss	Formal proof of the phased write dual port memory wrapper	commit \| commitdiff \| tree
2022-04-02	Cesar Strauss	Implement transparent read ports on the phased write...	commit \| commitdiff \| tree
2022-04-02	Cesar Strauss	Implement and test a "phased write port" memory	commit \| commitdiff \| tree
2022-03-27	Cesar Strauss	Finish the SRAM formal proof by implementing induction	commit \| commitdiff \| tree
2022-03-26	Cesar Strauss	Add formal verification of the single port memory block	commit \| commitdiff \| tree
2022-03-13	Cesar Strauss	Simulate some read/write/modify operations on the SRAM...	commit \| commitdiff \| tree
2022-03-13	Cesar Strauss	Add a Single R/W Port SRAM model	commit \| commitdiff \| tree
2022-03-06	Cesar Strauss	Copy the startup delay from issuer.py to inorder.py	commit \| commitdiff \| tree
2022-01-03	Cesar Strauss	On inorder.py, after Execute, update the PC and go...	commit \| commitdiff \| tree
2021-12-28	Cesar Strauss	Add an --inorder option to test_issuer.py	commit \| commitdiff \| tree
2021-12-27	Cesar Strauss	Fix indentation	commit \| commitdiff \| tree
2021-12-23	Cesar Strauss	Remove extra wait on core_stop_o at end of Execute.	commit \| commitdiff \| tree
2021-12-23	Cesar Strauss	Re-enable core stopped signal when stopped.	commit \| commitdiff \| tree
2021-09-19	Cesar Strauss	Fix rel_o/go_i signal names	commit \| commitdiff \| tree
2021-09-19	Cesar Strauss	Replace "Display" with "print" on simulation process	commit \| commitdiff \| tree
2021-09-19	Cesar Strauss	Fix import	commit \| commitdiff \| tree
2021-09-18	Cesar Strauss	Use a pre-compiled version of maturin	commit \| commitdiff \| tree
2021-09-13	Cesar Strauss	Save Gitlab runner cache, even on a failed test	commit \| commitdiff \| tree
2021-09-08	Cesar Strauss	Monitor exceptions, re-decoding the instruction in...	commit \| commitdiff \| tree
2021-09-08	Cesar Strauss	Monitor the exception input to PowerDecoder2	commit \| commitdiff \| tree
2021-09-08	Cesar Strauss	Remove default argument for dict.get()	commit \| commitdiff \| tree
2021-09-07	Cesar Strauss	Fix typo.	commit \| commitdiff \| tree
2021-08-17	Cesar Strauss	Enable LD/ST exception test case	commit \| commitdiff \| tree
2021-08-17	Cesar Strauss	Clear operand latch on a terminating condition	commit \| commitdiff \| tree
2021-08-17	Cesar Strauss	Add exc_o.happened to the conditions for terminating...	commit \| commitdiff \| tree
2021-08-17	Cesar Strauss	Fix activation of cancel signal	commit \| commitdiff \| tree
2021-08-16	Cesar Strauss	Adjust PortInterface traces according to MMU option	commit \| commitdiff \| tree
2021-07-10	Cesar Strauss	Show some usage of PortInterface in action	commit \| commitdiff \| tree
2021-07-10	Cesar Strauss	Add new traces to the GTKWave document	commit \| commitdiff \| tree
2021-07-10	Cesar Strauss	Add operand producers to the parallel LDST Compunit...	commit \| commitdiff \| tree
2021-07-10	Cesar Strauss	Detect unexpected operand fetches and produced results	commit \| commitdiff \| tree
2021-07-07	Cesar Strauss	Start of a GTKWave document for the LDST CompUnit parallel...	commit \| commitdiff \| tree
2021-07-04	Cesar Strauss	Beginning of a class to make a parallel test case for...	commit \| commitdiff \| tree
2021-06-06	Cesar Strauss	Start a new self-contained test suite for LDSTCompUnit	commit \| commitdiff \| tree
2021-05-22	Cesar Strauss	Remove redundant build step	commit \| commitdiff \| tree
2021-05-22	Cesar Strauss	Include missing step in automated build	commit \| commitdiff \| tree
2021-05-22	Cesar Strauss	Move the reset code outside of the sub-test	commit \| commitdiff \| tree
2021-05-01	Cesar Strauss	Add GTKWave documents to each DCache unit test	commit \| commitdiff \| tree
2021-04-25	Cesar Strauss	Shift-out skipped mask bits for both crpred and intpred	commit \| commitdiff \| tree
2021-04-22	Cesar Strauss	Implement CR predication	commit \| commitdiff \| tree
2021-04-21	Cesar Strauss	CR sub-fields are stored in MSB0 order	commit \| commitdiff \| tree
2021-04-21	Cesar Strauss	Add CR predication test case for TestIssuer	commit \| commitdiff \| tree
2021-04-21	Cesar Strauss	Fix comment in CR predication test case	commit \| commitdiff \| tree
2021-04-21	Cesar Strauss	Fix sense of "invert" signal	commit \| commitdiff \| tree
2021-04-17	Cesar Strauss	Implement 1<<r3 directly by a shift	commit \| commitdiff \| tree
2021-04-10	Cesar Strauss	Implement 1<<r3 predicate mode	commit \| commitdiff \| tree
2021-04-10	Cesar Strauss	Add 1<<r3 test cases to TestIssuer	commit \| commitdiff \| tree
2021-04-10	Cesar Strauss	Add test cases for 1<<r3 predication	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Make the VL loop reentrant in HDL	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Add a HDL test case, where we start at the middle of...	commit \| commitdiff \| tree
2021-04-06	Cesar Strauss	Start the test case from a point where the predicate...	commit \| commitdiff \| tree
2021-04-04	Cesar Strauss	Add test case for reentrant VL loop	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Reminder for a possible hardware optimization	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Be more precise when using a one-bit constant	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add test case with all mask bits equal to zero	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add a test case for integer single predication	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Disallow unknown encmodes in SVP64 Assembly	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Enable remaining disabled test cases	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Allow the Simulator to handle back-to-back signaling...	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Signal the simulator when completing a VL loop	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-03	Cesar Strauss	Add twin predication test	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	End VL loop as soon as either src/dst step reaches VL	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Add VEXPAND test case for the ISA Simulator	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Add VCOMPRESS test case for the ISA Simulator	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Put sanity check inside the existing '2Pred' case,...	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Enforce explicit src/dest masks on CR twin-predication	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Disallow mixing of sm=xx and/or dm=xx with m=xx on...	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Disallow dm=xx on single predication	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Fix typo	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Really enforce sm=xx not being allowed on single-pred	commit \| commitdiff \| tree
2021-04-02	Cesar Strauss	Keep mask mode flags separate	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Enable VCOMPRESS test case	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Add new twin predication case	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Adjust twin predication cases for the new syntax	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Skip leading zero bits on predicate masks	commit \| commitdiff \| tree
2021-03-30	Cesar Strauss	Memory port seems to have been renamed	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Move DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Move instruction decoding to after predication	commit \| commitdiff \| tree
2021-03-28	Cesar Strauss	Prepare to advance src/dst step after getting the predicate...	commit \| commitdiff \| tree
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