only add pc_i in DMI mode
[libresoc-litex.git] / libresoc / core.py
2021-12-23 Luke Kenneth Casso... only add pc_i in DMI mode
2021-09-24 Jacob LifshayMerge remote-tracking branch 'ngi-nix/master'
2021-09-19 Las SafinAdd more supported GCC triples
2021-06-09 Luke Kenneth Casso... sort out PLL connection, in and out of peripheral inter...
2021-06-09 Luke Kenneth Casso... try setting domain to "CPU"
2021-06-09 Luke Kenneth Casso... add PLL clock loop-back into CPU
2021-06-09 Luke Kenneth Casso... add PLL clock loop-back into CPU
2021-06-03 Luke Kenneth Casso... dummy PLL added with bypass, rename ref to ref_v due...
2021-05-26 Luke Kenneth Casso... remove wb err signal from sram4k
2021-05-22 Luke Kenneth Casso... match up PLL names
2021-05-22 Luke Kenneth Casso... match up PLL names
2021-05-22 Luke Kenneth Casso... rename vco_test_ana to pll_testout_o
2021-05-09 Luke Kenneth Casso... code-comments about ls180 imports
2021-04-18 Luke Kenneth Casso... sort out names
2021-04-18 Luke Kenneth Casso... whoops clk_sel_i renamed accidentally
2021-04-18 Luke Kenneth Casso... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth Casso... add SPBlock_512W64B8W.v to sources
2021-04-18 Luke Kenneth Casso... put imports into conditional blocks. makes core.py...
2021-04-08 Luke Kenneth Casso... reduce jtag data bus width to 32, to match litex
2021-04-05 Luke Kenneth Casso... sort out sdr and sdmmc OE pad drive, no longer one...
2021-04-01 Luke Kenneth Casso... disable PLL for litex build, new variant
2021-03-28 Luke Kenneth Casso... fix issues with port direction on several pads
2021-03-27 Luke Kenneth Casso... latest fighting with litex to get pad directions connec...
2021-03-25 Luke Kenneth Casso... debugging ls180 litex hell
2021-03-22 Luke Kenneth Casso... sort out naming of IOpads for bi-directional pins
2021-03-12 Luke Kenneth Casso... splitting out litex files from soc repo into separate...