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Add support for virtual priv register. (#59)
[riscv-isa-sim.git]
/
riscv
/
gdbserver.cc
2016-07-28
Tim Newsome
Add support for virtual priv register. (#59)
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2016-07-19
Tim Newsome
Make address translation work in 32-bit. (#58)
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2016-07-01
Tim Newsome
Remove debug printf that was cluttering up output.
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2016-06-28
Tim Newsome
Make gdbserver code work with small Debug RAM.
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2016-06-28
Tim Newsome
Support debugging 32-bit spike instances.
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2016-05-23
Tim Newsome
Turn off debugging.
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2016-05-23
Tim Newsome
Tell gdb we can handle large packets.
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2016-05-23
Tim Newsome
Fix writing odd numbers of bytes to odd addresses.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode don't update any regs.
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2016-05-23
Tim Newsome
Write test for downloading a mostly random program
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2016-05-23
Tim Newsome
Implement ebreak[mhsu].
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2016-05-23
Tim Newsome
Remove dependency on include file in my homedir.
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2016-05-23
Tim Newsome
Deal with escapes that gdb sends in binary data.
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2016-05-23
Tim Newsome
Halt when gdb user hits ^C.
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2016-05-23
Tim Newsome
Make sure to fence.i after setting/clearing a swbp
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2016-05-23
Tim Newsome
Implemented register writes.
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2016-05-23
Tim Newsome
Fix reading CSRs.
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2016-05-23
Tim Newsome
Single step appears to work.
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2016-05-23
Tim Newsome
Software breakpoints sort of work.
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2016-05-23
Tim Newsome
Fix off-by-two in general read registers.
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2016-05-23
Tim Newsome
Walk page tables to translate addresses.
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2016-05-23
Tim Newsome
Turn operation into a queue,
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2016-05-23
Tim Newsome
Remove unused code.
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2016-05-23
Tim Newsome
Save/restore mstatus, too.
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2016-05-23
Tim Newsome
Properly read s0/s1.
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2016-05-23
Tim Newsome
Implement memory writes.
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2016-05-23
Tim Newsome
Implement single memory read access.
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2016-05-23
Tim Newsome
Properly save/restore dpc, mcause, mbadaddr.
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2016-05-23
Tim Newsome
Exceptions in Debug Mode, stay in Debug Mode.
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2016-05-23
Tim Newsome
Read FP registers, and general CSRs*
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2016-05-23
Tim Newsome
Continue works well enough for DebugTest.test_exit
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2016-05-23
Tim Newsome
Refactor how we track in-progress operations.
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2016-05-23
Tim Newsome
gdb can attach and read the PC:
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2016-05-23
Tim Newsome
processor_t unfriends gdbserver_t.
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2016-05-23
Tim Newsome
Correctly read PC on halt.
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2016-05-23
Tim Newsome
Fix store to clear debug interrupt.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
When gdb connects, jump to Debug ROM and segfault.
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2016-05-23
Tim Newsome
Gutting direct-access gdb.
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2016-05-23
Tim Newsome
Add --gdb-port
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2016-05-23
Tim Newsome
Minor cleanup.
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2016-05-23
Tim Newsome
Update regnum handling to match gdb CSR changes.
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2016-05-23
Tim Newsome
Implement register writes.
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2016-05-23
Tim Newsome
Implement reading of CSRs.
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2016-05-23
Tim Newsome
Add some tests that pass and test something.
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2016-05-23
Tim Newsome
Flush icache when using swbps and report to gdb.
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2016-05-23
Tim Newsome
Software breakpoints seem to work.
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2016-05-23
Tim Newsome
Rewrite GPL'd code from OpenOCD.
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2016-05-23
Tim Newsome
Looks like single step works.
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2016-05-23
Tim Newsome
Add -H to start halted.
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2016-05-23
Tim Newsome
Implement binary memory write.
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2016-05-23
Tim Newsome
Now you can halt/continue from gdb.
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2016-05-23
Tim Newsome
Register read looks sane now.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Hack to the point where gdb reads a register.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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projects / riscv-isa-sim.git / history