| 2022-01-08 |
Luke Kenneth Casson... | start adding in mis-aligned LD/ST support into LoadStore1
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| 2022-01-07 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add missing MSRSpec import
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commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add msr_o to issuer in microwatt_compat mode
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commit | commitdiff | tree |
| 2022-01-06 |
Luke Kenneth Casson... | double the number of lines in the L1 D/I-Cache to match...
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commit | commitdiff | tree |
| 2022-01-06 |
Luke Kenneth Casson... | add SECOND_REQ state to loadstore.py, not yet implemented
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commit | commitdiff | tree |
| 2022-01-05 |
Luke Kenneth Casson... | add easy-to-access debug reporting of instruction and PC
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commit | commitdiff | tree |
| 2022-01-05 |
Luke Kenneth Casson... | use microwatt-specific PLRU due to bug in nmutil version
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commit | commitdiff | tree |
| 2022-01-04 |
Luke Kenneth Casson... | fix DriverConflict over MSR write in Issuer/Core by...
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commit | commitdiff | tree |
| 2022-01-04 |
Luke Kenneth Casson... | remove FetchFSM from TestIssuer (it served its purpose...
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| 2022-01-03 |
Luke Kenneth Casson... | doh, bus-hack was the wrong way round. *output* the...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | sigh, microwatts wishbone bus usage is non-wishbone...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | sigh have to allow external clocks and reset mess even...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | give module appropriate top-level name in microwatt...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | add missing ext_irq signal to testissuer in microwatt...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | adding an extra option to issuer_verilog.py to be able...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | bring external irq out for microwatt-compatible mode...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | stop display of LDSTCompUnit debug info on every cycle
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commit | commitdiff | tree |
| 2021-12-30 |
Luke Kenneth Casson... | rename nia to cia in MMU input record and mmu FSM
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commit | commitdiff | tree |
| 2021-12-28 |
Luke Kenneth Casson... | add misaligned mmu.bin test 5 notes: currently LoadStore1...
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commit | commitdiff | tree |
| 2021-12-27 |
Luke Kenneth Casson... | found bug in mmu with calculating addrsh, should have...
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commit | commitdiff | tree |
| 2021-12-27 |
Luke Kenneth Casson... | add mmu.py microwatt mmu.bin test4 page table
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commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | good grief, finally tracked down a piece of missing...
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commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | whoops, using variable RegStage0 in dcache stage_0...
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commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | missed reset of d_valid in dcache.py and missed that its
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commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | rename addr to raddr in LoadStore1 to avoid conflict...
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | add mmu.bin test2 to much simpler test_loadstore1.py
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | move msr in test_loadstore1.py outside of conditional...
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | move microwatt mmu.bin test 3 page table to test pagetables...
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | wait for MMU "done" when setting PRTBL and PIDR
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commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | add microwatt mmu.bin regression test test_mmu_3
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commit | commitdiff | tree |
| 2021-12-24 |
Luke Kenneth Casson... | enable instruction redirect in mmu ifetch test
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commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | somehow managed to miss out setting r1.forward_valid1...
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commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | uniquify names in dcache.py
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commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | allow MSR reset to default to a value set by issuer_verilog.py
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commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | pass in msr_reset to issuer_verilog.py
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commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | add ability to set the reset values of RegFileArray
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | only use a single variable for ack adjusting in dcache.py
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | fix issues with running core in DMI "stopped" status...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | when setting DSISR in LoadStore1 use correct load bit...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | use correct X-Form L field in OP_MTMSRD
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | check problem state in OP_MTMSRD from original reg...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops, use MSR.IR for I-Cache fetch!
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove unneeded state in LoadStore1
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on exception WAIT_MMU ACK in...
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear out instr_fault when exception is thrown
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on idle/valid in Loadstore1
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | ooo far too late at night to be doing this
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove bus_ack (found bug in Simulation, sorted)
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commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | bug in mmu setting radix tree size with one extra bit
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | continue to assert PC in FetchFSM if needed
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | enable I-Cache wishbone memory type in issuer_verilog...
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | whoops issuer_verilog.py enabling mmu has to pass microwatt_mmu
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | for each unit test case in test_issuer_mmu_data_path...
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | test_issuer_mmu_data_path.py needs to use wb_get because of
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu code-comments
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | comments
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | use prtbl in proc_tbl_wait in mmu
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commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu.py comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | set up DAR correctly in unit tests, added set_ldst_spr...
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | unit tests for SPRs when MMU enabled,
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | code-comments in MMU
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | prefer not to invert when doing if/else.
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add RTPDE - Radit Tree Page Directory Entry - Record...
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add (and ues) PRTBL Record in MMU
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commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | create PGTBL Record and use it in MMU page_table_idle
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add hard stop address in ifetch unit test, bit of a...
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | set terminate if core terminate requested
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add DMI STOPADDR register and use it in HDLRunner to...
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commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | break out when core is stopped in HDLRunner
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add link to XICS bugreport
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | sort out reset signalling after tracking down Simulation...
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add icache/dcache/mmu unit test for TestIssuer
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | get instructions to re-run in issuer after I-Cache...
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | forgot to connect up I-Cache to MMU
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | move connection of bus.stall in icache.py,
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tidyup
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tlb_req_index is TLB_BITS long not TLB_SIZE
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops, a Simulation bug, dcache bus ack Signal needed...
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | give names to MMU records
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | set_mmu_spr was using the slow-SPR index for the regfile
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops remove duplicate code (cut/paste error) no harm...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more unneeded code
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | read MSR.PR and MSR.DR and update ICache priv/virt...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more of SVP64 from TestIssuerInternalInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove update of pc, msr and svstate from TestIssuerInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move update of pc, msr and svstate into TestIssuerBase
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | comment-out TestIssuerInternalInorder for now
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move alternative TestIssuerInternalInOrder to new file
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | split out common elaboratable code from TestIssuer,
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | big split-out of common functions in TestIssuer to...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | simplifying / tidyup of TestIssuer to get CoreState
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | sort out MSR, read/write in same way as PC/SVSTATE...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | whoops accidentally commented out setup of instructions
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