Added commit logging (--enable-commitlog). Also fixed disasm bug.
[riscv-isa-sim.git] / riscv / processor.cc
2013-09-27 Christopher CelioAdded commit logging (--enable-commitlog). Also fixed...
2013-09-23 Scott Beamerfixes compile bug for not being able to find std::logic...
2013-09-11 Andrew WatermanImplement zany immediates
2013-08-18 Andrew WatermanRenumber PCRs
2013-08-13 Andrew WatermanImplement RoCC and add a dummy RoCC
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-26 Andrew WatermanRip out Hwacha for now
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-07-22 Andrew WatermanAdd xspike program
2013-04-25 Andrew Watermanuse inttypes macros to print uint64_t
2013-04-24 Yunsup Leefixes to correctly simulate the vector unit
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-30 Andrew Watermanignore writes to SR IP field
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-03-26 Andrew Watermanexpose pending interrupts in status register
2013-02-13 Andrew Watermanclean up fetch-execute loop a bit
2012-11-13 Yunsup Leefix vector code simulation problem, turn on SR_U64
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-08-02 Andrew Watermannew tohost/fromhost semantics
2012-07-23 Andrew Watermancorrect HTIF reset behavior
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-03-20 Andrew Watermanabstract regfile behind object
2011-12-11 Yunsup Leefix utidx assign bug, make ut code execute faster
2011-11-12 Your NameRemove dependence on binutils
2011-11-11 Andrew WatermanUse new compiler toolchain's disassembler
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
2011-05-31 Andrew Waterman[sim] minor sim cleanup
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-23 Andrew Waterman[sim,xcc] add rdcycle/rdtime/rdinstret
2011-05-19 Yunsup Lee[sim] change default hwvl
2011-05-19 Yunsup Lee[sim] vlen calc reflects the hardware
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support
2011-05-14 Andrew Waterman[sim] initial support for virtual memory
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-12 Andrew Waterman[xcc,sim,opcodes] more rvc instructions and bug fixes
2011-04-10 Yunsup Lee[sim] add disable option for vector
2011-04-10 Yunsup Lee[sim] set SR_EV for uts
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-04-10 Andrew Waterman[xcc,pk,sim,opcodes] added first RVC instruction
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] Tweaked FP encoding
2010-10-26 Yunsup Lee[pk,sim,xcc] get rid of at register, introduce tp register
2010-10-16 Andrew Waterman[pk, sim] added FPU emulation support to proxy kernel
2010-10-05 Andrew Waterman[xcc,sim] eliminated vectored traps
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-09 Andrew Waterman[pk, sim] added interrupt support to sim; added timer...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-07 Yunsup Lee[sim] fix stdint.h __STDC_LIMIT_MACROS problem
2010-09-07 Andrew Waterman[sim, xcc] branches now have 2-byte-aligned displacements
2010-09-07 Andrew Waterman[sim, xcc] bthread threading model exposed; insn encodi...
2010-08-24 Andrew Waterman[xcc] argc/argv work for 32b programs
2010-08-24 Andrew Waterman[sim] privileged mode support for 32-bit operation
2010-08-10 Andrew Waterman[xcc,sim] implement FP using softfloat
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-29 Andrew Waterman[sim,xcc] Changed instruction format to RISC-V
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure