autoreconf 126beb482ff6 ("Install pkg-config files for Spike")
[riscv-isa-sim.git] / riscv /
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-30 Andrew WatermanFix commit log for CSR instructions
2015-04-26 Andrew WatermanFix I$ simulator hit count
2015-04-14 Andrew WatermanMerge pull request #18 from wsong83/master
2015-04-13 Wei Songfix cache line index offset in cachesim.cc
2015-04-04 Andrew WatermanCheck for F extension when accessing FCSR
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-04-02 Andrew WatermanSimplify RV32 comparisons
2015-03-31 Andrew WatermanAllow writing mstatus.fs even if FPU isn't present
2015-03-31 Andrew WatermanImplement RVC draft
2015-03-27 Andrew WatermanSerialize counters without throwing C++ exceptions
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-26 Andrew WatermanUpdate state.pc on every instruction
2015-03-21 Andrew WatermanFor misaligned fetch, set mepc = addr of branch/jump
2015-03-17 Yunsup Leebugfix, mbadaddr should be writable
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-16 Yunsup Leebugfix in raising accelerator interrupts
2015-03-14 Andrew WatermanDon't set dirty/referenced bits w/o permission
2015-03-13 Andrew WatermanUse hcall instead of mcall
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-02-08 Andrew WatermanUse xlen, not xprlen, to refer to x-register width
2015-01-27 Christopher CelioFixed masking/casting logic in commit log printf.
2015-01-26 Andrew WatermanFix commit log
2015-01-09 Stephen TwiggFix bug where C compiler used instead of C++ for autoco...
2015-01-03 Andrew WatermanRequire 4-byte instruction alignment until RVC is reimp...
2015-01-03 Andrew WatermanOn misaligned fetch, set EPC to target, not branch...
2015-01-02 Andrew WatermanReduce dependences on auto-generated code
2014-12-05 Andrew WatermanSupport 2/4/6/8-byte instructions
2014-12-05 Andrew WatermanSet badvaddr on instruction page faults
2014-12-03 Andrew WatermanUpdate register names to match new ABI
2014-12-01 Andrew WatermanImplement timer faithfully
2014-11-25 Andrew WatermanFactor out the dummy RoCC accelerator
2014-11-22 Yunsup LeeRevert "Enable support for the four custom instructions"
2014-11-20 Andrew WatermanAdd missing makefile dependence
2014-11-07 Andrew WatermanMerge pull request #8 from arunthomas/dummy_rocc_test
2014-10-30 Arun Thomasdummy-rocc-test build fix
2014-10-24 Yunsup LeeMerge pull request #4 from arunthomas/custom_inst
2014-10-23 Arun ThomasEnable support for the four custom instructions
2014-09-27 Andrew WatermanAvoid some unused variable warnings
2014-09-27 Andrew WatermanAvoid use of __int128_t
2014-09-21 Scott BeamerMerge pull request #2 from arunthomas/build_fix
2014-09-21 Arun ThomasUpdate riscv.ac to set CPPFLAGS with fesvr include...
2014-08-26 Scott Beamerclean up warnings from clang
2014-08-15 Christopher CelioAdded PC histogram option.
2014-08-08 Andrew WatermanSupport uarch counters (degenerately)
2014-07-25 Scott Beameradded support for register convention names in debug...
2014-07-08 Andrew WatermanDisallow access to FCSR when FP is disabled
2014-07-07 Andrew WatermanUse precompiled headers to speed up compilation
2014-07-07 Andrew WatermanMinor refactoring
2014-06-13 Christopher CelioCommit log now prints while interrupts are enabled.
2014-06-13 Andrew WatermanOnly print commit log if instruction commits
2014-06-12 Andrew WatermanSet status.u64 to true on boot
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-04-03 Stephen TwiggSync encoding in opcodes
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-15 Andrew Watermanspeed up compilation a bit
2014-03-12 Andrew WatermanNew FP encoding
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-25 Yunsup Leeadd extensions to riscv-dis for better disassembly
2014-02-15 Andrew WatermanRenumber uarch CSRs into custom CSR space
2014-02-14 Andrew WatermanFix I$ simulator not making forward progress
2014-02-12 Andrew WatermanFix commit log when !debug
2014-02-11 Andrew WatermanRevert to old AUIPC definition
2014-02-07 Andrew WatermanClear EVEC LSBs, which kindly prevents a segfault
2014-02-06 Yunsup Leecommit missing definitions for uarch counters
2014-02-01 Andrew WatermanFix linking on Darwin
2014-01-28 Andrew WatermanForce extension loaders to be linked in
2014-01-27 Andrew WatermanEnable runtime loading of dynamic library with --extlib
2014-01-27 Andrew WatermanEliminate hwacha <-> riscv circular dependence
2014-01-26 Andrew WatermanMerge softfloat_riscv into softfloat
2014-01-24 Andrew WatermanRequire libdl for dynamic linking at runtime
2014-01-24 Andrew WatermanDisassemble amoxor
2014-01-24 Andrew WatermanBuild and use shared libraries only
2014-01-24 Andrew WatermanBuild and use shared libraries
2014-01-24 Andrew WatermanHandle CSR permissions correctly
2014-01-22 Andrew WatermanUse auto-generated trap cause numbers
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-16 Andrew WatermanInitialize tohost and fromhost to zero
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-12-09 Andrew WatermanNew RDCYCLE encoding
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-25 Quan NguyenMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-11-21 Yunsup Leefix slli/slliw encoding bug
2013-11-06 Yunsup Leeadd accelerator disabled cause
2013-11-06 Yunsup Leecorrectly trap when SR_EA is disabled
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-29 Andrew WatermanPass target machine's return code back to OS
2013-10-28 Quan NguyenAdd missing fcvt opcodes through riscv-opcodes
2013-10-19 Yunsup Leeclean up SR_EA, the enable accelerator bit in status reg
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-10-18 Quan NguyenAdd empty opcode header files for half-precision
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-18 Yunsup Leefix custom-1 rocc encoding
2013-10-16 Yunsup Leeuse reset virtual method
2013-10-16 Yunsup Leefix missing null check when there's no extension
2013-10-16 Yunsup Leerevamp hwacha; now runs in physical mode
2013-10-15 Stephen TwiggPropogate the reset call to the extensions as well...
2013-10-15 Stephen TwiggFix bug where xs2 was not being properly respected.
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