Added PC histogram option.
[riscv-isa-sim.git] / riscv / insns /
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-11 Andrew WatermanRevert to old AUIPC definition
2014-01-21 Quan NguyenMerge branch 'confprec'
2013-12-09 Andrew WatermanNew RDCYCLE encoding
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-25 Quan NguyenMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-18 Quan NguyenAdd empty opcode header files for half-precision
2013-10-16 Yunsup Leerevamp hwacha; now runs in physical mode
2013-09-27 Andrew WatermanUse WRITE_RD/WRITE_FRD macros to write registers
2013-09-21 Andrew WatermanUpdate ISA encoding and AUIPC semantics
2013-09-11 Andrew WatermanAdd AMOXOR
2013-09-11 Andrew WatermanImplement zany immediates
2013-09-10 Andrew WatermanAdd rd field to JAL; drop J
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-08-08 Andrew WatermanIgnore JALR's effective address LSB
2013-08-08 Andrew WatermanRename MTFSR/MFFSR to FSSR/FRSR
2013-08-01 Quan NguyenFix eret (again)
2013-07-31 Andrew WatermanFix dumb ERET bug
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-27 Andrew WatermanRename MFTX/MXTF to FMV
2013-07-26 Andrew WatermanRip out Hwacha for now
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-25 Andrew WatermanRemove JALR static hints
2013-04-17 Andrew Watermanadd AUIPC insn; remove RDNPC insn
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-08-02 Andrew Watermannew tohost/fromhost semantics
2012-03-24 Andrew Watermannew supervisor mode
2012-03-20 Andrew Watermanmake NaN behavior consistent with hardfloat
2012-03-19 Andrew Watermanupdate vector fences
2012-03-18 Yunsup Leeclean up vector exception instructions
2012-03-14 Yunsup Leeadd more instructions for vector exception handling
2012-03-14 Yunsup Leeadd vvcfg,vtcfg
2012-03-13 Yunsup Leeopcodes cleanup
2012-03-03 Yunsup Leeadd place holders for instructions to handle vector...
2012-02-20 Andrew Watermanfixed a bug in remu[w]
2012-02-16 Andrew Watermanreimplement div[u][w]/rem[u][w]
2012-01-30 Yunsup Leefix divide by zero bugs
2011-12-11 Yunsup Leefix utidx assign bug, make ut code execute faster
2011-11-11 Andrew WatermanChanged MFTX to use rs1 for its source
2011-11-11 Andrew WatermanChanged supervisor mode
2011-10-19 Yunsup LeeMerge branch 'master' of github.com:ucb-bar/riscv-isa-sim
2011-10-19 Yunsup Leefix vf
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
2011-06-06 Andrew Waterman[sim] fix writeback after ipi clearing
2011-06-05 Andrew Waterman[sim] add ability to clear IPIs
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-23 Andrew Waterman[sim,xcc] add rdcycle/rdtime/rdinstret
2011-05-19 Andrew Waterman[sim] more fp<->int fixes
2011-05-19 Andrew Waterman[sim] more fp conversion bugs fixed
2011-05-18 Andrew Waterman[sim] fixed fcvt rounding bugs
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support
2011-05-16 Yunsup Lee[sim,xcc] change cond. mov inst format, add implementation
2011-05-16 Yunsup Lee[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec...
2011-05-14 Andrew Waterman[sim] stubs for perfctr instructions
2011-04-25 Andrew Waterman[xcc,sim,opcodes] added c.addiw
2011-04-24 Andrew Waterman[xcc,sim,opcodes] added more RVC instructions
2011-04-24 Andrew Waterman[sim] fixed divw/remw crashing simulator
2011-04-19 Andrew Waterman[xcc,sim] rv64 'w' instruction semantics changed
2011-04-19 Andrew Waterman[xcc,sim,opcodes] added rvc conditional branches
2011-04-17 Andrew Waterman[sim] removed undefined behavior for non-canonical...
2011-04-15 Andrew Waterman[sim] fixed jalr immediate bug
2011-04-13 Andrew Waterman[xcc,pk,sim] added privileged cflush instruction
2011-04-12 Andrew Waterman[xcc,sim] rvc loads and stores
2011-04-12 Andrew Waterman[xcc,sim,opcodes] more rvc instructions and bug fixes
2011-04-10 Yunsup Lee[sim] add vector traps to vector instructions
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-04-10 Andrew Waterman[xcc, sim] added rvc insn c.li; misc fixes
2011-04-10 Andrew Waterman[xcc,pk,sim,opcodes] added first RVC instruction
2011-04-08 Andrew Waterman[sim] fixed multiply-high in rv32
2011-04-05 Yunsup Lee[opcodes,pk,sim,xcc] fix vector mem instruction format...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add leftover vector instructions...
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add vector mem instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add stop,utidx instructions
2011-04-04 Yunsup Lee[opcodes,pk,sim,xcc] add fence instructions for vector...
2011-03-30 Andrew Waterman[xcc] fixed bug in amo{maxu,minu}.w
2011-03-26 Andrew Waterman[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-03-18 Andrew Waterman[sim] LWU now illegal in RV32
2011-02-15 Andrew Waterman[xcc,opcodes,pk,sim] krste's re-renaming spree
2011-02-15 Andrew Waterman[xcc,sim,opcodes] removed mtflh/mffl/mffh
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-02-02 Andrew Waterman[sim,xcc,opcodes] added back mtflh.d
2011-02-02 Andrew Waterman[xcc,opcodes,pk,sim] cleanup to FP ISA
2011-01-27 Andrew Waterman[sim] changed divide-by-0 semantics
2011-01-26 Andrew Waterman[sim,opcodes] add mulhsu instruction
2011-01-26 Andrew Waterman[opcodes,pk,sim,xcc] great renumbering of 2011, part...
2011-01-21 Andrew Waterman[sim, pk, xcc, opcodes] great instruction renaming...
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2011-01-17 Andrew Waterman[opcodes, pk, sim, xcc] removed nor, normalized macros...
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