| 2021-06-09 |
Luke Kenneth Casson... | add in/out of ref_clk and pllclk_clk when PLL enabled
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | comment out domains that have already been created
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | no, do not assign clock to clock!
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | rename ref to ref_v in PLL due to ref being a verilog...
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | sort out PLL domains but bypass PLL due to lack of...
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | use DomainRenamer on all sub-components of TestIssuer
|
commit | commitdiff | tree |
| 2021-06-03 |
Luke Kenneth Casson... | make core_rst a member of TestIssuerInternal
|
commit | commitdiff | tree |
| 2021-05-27 |
Luke Kenneth Casson... | adjust PLL connections looking for coriolis2 issue
|
commit | commitdiff | tree |
| 2021-05-27 |
Luke Kenneth Casson... | corrections on spblock ack
|
commit | commitdiff | tree |
| 2021-05-27 |
Luke Kenneth Casson... | classic wishbone mode: must not do ack if already acked
|
commit | commitdiff | tree |
| 2021-05-26 |
Luke Kenneth Casson... | arse. PLL test_issuer clk_sel_i accidentally only 1...
|
commit | commitdiff | tree |
| 2021-05-26 |
Luke Kenneth Casson... | remove err feature from sram4k wb
|
commit | commitdiff | tree |
| 2021-05-26 |
Luke Kenneth Casson... | add ldst PortInterface misalign unit test (underway)
|
commit | commitdiff | tree |
| 2021-05-26 |
Luke Kenneth Casson... | rename PLL signals
|
commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | whoops sort out name of SPBlock RAM
|
commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | change name of submodule to real_pll
|
commit | commitdiff | tree |
| 2021-05-24 |
Luke Kenneth Casson... | match up PLL names
|
commit | commitdiff | tree |
| 2021-05-22 |
Luke Kenneth Casson... | update submodule
|
commit | commitdiff | tree |
| 2021-05-22 |
Luke Kenneth Casson... | update PLL to use Instance
|
commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | add radix MMU "miss" test
|
commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | clear out request data on return to idle
|
commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | sort out LoadStore1 misalignment FSM, also required...
|
commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | remove minerva units previously missed in cleanout
|
commit | commitdiff | tree |
| 2021-05-14 |
Luke Kenneth Casson... | add misaligned load through MMU (which is incorrectly...
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | minor rework of wb_get, make generic
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | added STORE test in test_ldst_pi.py, and it worked...
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | update comments in issuer.py regarding a 4th FSM
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | yet more debug log stuff for DCache, this time on CacheRam...
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | fix wb_get error where data was being corrupted
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | add read at different locations in test_ldst_pi.py
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | add some data for MMU to actually look up
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | ha, hilarious: swapped TLBUpdate output sizes db_out...
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | whoops TLBIE must *clear* the valid bit not set it...
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | more debug Display in dcache.py
|
commit | commitdiff | tree |
| 2021-05-13 |
Luke Kenneth Casson... | putting in a lot more debug print statements in DCache...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | add dcache tlb / pte test
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | set m_out.load from ldst_r(egister) in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | move dcache unit test to separate test_dcache.py
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | experimentation with MMU-enabled LoadStore1 through...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | add debug info, update comments, disable dcache in...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | start doing virtual memory queries via PortInterface...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whoops missing default zero (no idea how)
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | addcomments for MMU PortInterface test (how it, um...
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | bit of a hack to get test_mmu_dcache_pi.py operational.
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2021-05-12 |
Luke Kenneth Casson... | no need for sel0
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | pass through MSR.PR through PortInterface, into LoadStore1
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | connect MSR.PR to PortInterface in LDSTCompUnit
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add msr_pr bit in PortInterface
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | add MSR to LD/ST Input Record
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | comment tidyup
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | must also pass through instruction fault exception...
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | whoops names changed in MMU FSM
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | tidyup comments and remove LoadStore COMPLETE state
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | cleanup on exception setting
|
commit | commitdiff | tree |
| 2021-05-11 |
Luke Kenneth Casson... | rename LoadStore1 data structures back to microwatt...
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add block for MMU activation to LoadStore1
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | whoops, indentation issue on m.If/m.Else in dcache.py
|
commit | commitdiff | tree |
| 2021-05-10 |
Luke Kenneth Casson... | add links to set associative image, and bugreport
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments on translation of MMU_LOOKUP
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | install MMU_LOOKUP vhdl to be translated to nmigen
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | move (unused) ACK_WAIT code into FSM
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comments in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove invalid setting of d_in.valid from self.mmureq
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | no SECOND_REQ
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | remove SECOND_REQ
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add comment about LD/ST exception needs copying into...
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | run LD/ST Exception test case for MMU
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add MMU bugtracker link
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | git submodule update
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | update code-comments
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add in alignment exception capture/reporting in LoadStore1
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | preference is to create a temp variable for comb and...
|
commit | commitdiff | tree |
| 2021-05-09 |
Luke Kenneth Casson... | add misalign flag to PortInterfaceBase
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | LoadStore1 tidyup
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | transferring more over to LoadStore FSM
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | start putting state info into LoadStore1, slowly putting...
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add LoadStore State enum
|
commit | commitdiff | tree |
| 2021-05-08 |
Luke Kenneth Casson... | add bugreport link to mmu
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | start setting DSISR bits but commented out
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | update comments and docstrings
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops, import error
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move LoadStore1 class to soc.fu.ldst.loadstore
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops was still copying output over in CommonOutputStage
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | how we managed to get this far without noticing that...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move dsisr and dar into LoadStore1
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | move zero-dest-pred in Common Output Stage to not copy...
|
commit | commitdiff | tree |
| 2021-05-07 |
Luke Kenneth Casson... | whoops setup of core.sv_pred_sm/dm not indented and...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | whoops disabled tests agaaaaain
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass relevant predicate mask bits through to Decoders...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | add in predicate mask bit detection when zeroing is...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | pass SVP64 ReMap field through to core and then on...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | moved exts* SVP64 unit tests to a different location
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | argh someobe falsely stated in the README that LibreSOC...
|
commit | commitdiff | tree |
| 2021-05-06 |
Luke Kenneth Casson... | if zeroing is set, put zero into input or output as...
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | simplify README.md so that it gets submitted to pypi
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | mark long description type as markdown
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | update NEWS.txt
|
commit | commitdiff | tree |
| 2021-05-05 |
Luke Kenneth Casson... | add libresoc-openpower-isa to setup.py dependencies
|
commit | commitdiff | tree |
| next |
projects / soc.git / search