Rename badaddr to tval
[riscv-isa-sim.git] / riscv / processor.h
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-23 Andrew Waterman[sim,xcc] add rdcycle/rdtime/rdinstret
2011-05-19 Yunsup Lee[sim] vlen calc reflects the hardware
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2010-10-26 Yunsup Lee[pk,sim,xcc] get rid of at register, introduce tp register
2010-10-05 Andrew Waterman[xcc,sim] eliminated vectored traps
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-09 Andrew Waterman[pk, sim] added interrupt support to sim; added timer...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-07 Yunsup Lee[sim] yet another fix stdint.h __STDC_LIMIT_MACROS...
2010-09-07 Andrew Waterman[sim, xcc] added PCRs to replace k0 and k1
2010-09-07 Andrew Waterman[sim, xcc] bthread threading model exposed; insn encodi...
2010-08-24 Andrew Waterman[sim] privileged mode support for 32-bit operation
2010-08-10 Andrew Waterman[xcc,sim] implement FP using softfloat
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure