Rename badaddr to tval
[riscv-isa-sim.git] / riscv / processor.h
2017-11-27 Andrew WatermanRename badaddr to tval
2017-11-27 Andrew WatermanRename sptbr to satp
2017-11-16 Andrew WatermanMerge pull request #156 from p12nGH/noncontiguous_harts
2017-11-10 Andrew WatermanH-mode no longer exists
2017-11-10 Andrew WatermanMPP is now WARL
2017-10-20 Andrew WatermanFix commit-log for Q extension, and for RV32 (#143)
2017-09-21 Tim NewsomeFix corner case in repeated execution (#127)
2017-08-10 Tim NewsomeMerge pull request #117 from riscv/multicore_debug
2017-08-07 Tim NewsomeFix multicore debug.
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-04-18 Megan Wachsdebug: Checkpoint which somewhat works with OpenOCD...
2017-04-18 Megan Wachsdebug: Move things around, but addresses now conflict...
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-03-22 Wesley W. Terpstrariscv: replace rtc device with a real clint implementation
2017-02-25 Andrew WatermanNew counter enable scheme
2017-02-11 Tim NewsomeEntering debug mode now jumps to "dynamic rom"
2017-02-10 Tim NewsomeImplement hartstatus field.
2017-02-07 Tim NewsomeMerge pull request #83 from bacam/gdb-protocol-fixes
2017-02-03 Andrew WatermanFix interrupt delegation for coprocessors
2016-09-10 Andrew Watermanallow MAFDC bits in MISA to be modified
2016-09-02 Andrew WatermanMerge pull request #62 from riscv/trigger
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-08-31 Tim NewsomeRename tdata[0-2] to tdata[1-3].
2016-08-29 Tim NewsomeRename tdata0--tdata2 to tdata1--tdata3.
2016-08-27 Andrew WatermanAdd (degenerate) performance counter facility
2016-08-26 Andrew Watermanpartially update spike to newer debug spec
2016-08-26 Andrew WatermanFix spike interactive (-d) mode
2016-08-22 Tim NewsomeImplement address and data triggers.
2016-08-17 Andrew WatermanAllow mstatus.MPP to store bad values; instead, validat...
2016-07-28 Tim NewsomeAdd support for virtual priv register. (#59)
2016-06-29 Andrew WatermanDisassemble RVC instructions based on XLEN
2016-06-23 Andrew WatermanRemove legacy HTIF; implement HTIF directly
2016-06-23 Andrew WatermanFix paddr_bits computation prior to VM setup
2016-05-23 Tim NewsomeMake -H halt the core right out of reset.
2016-05-23 Tim NewsomeSingle step appears to work.
2016-05-23 Tim Newsomeprocessor_t unfriends gdbserver_t.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeWhen gdb connects, jump to Debug ROM and segfault.
2016-05-23 Tim NewsomeGutting direct-access gdb.
2016-05-23 Tim NewsomeAdd writing to DCSR, DPC, DSCRATCH.
2016-05-23 Tim NewsomeFlush icache when using swbps and report to gdb.
2016-05-23 Tim NewsomeLooks like single step works.
2016-05-23 Tim NewsomeNow you can halt/continue from gdb.
2016-05-23 Tim Newsomegdb can now read spike memory.
2016-05-02 Andrew WatermanRemove tohost/fromhost registers
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-03-02 Andrew WatermanAdd counter-enable registers
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanNew definitions of misa/marchid/mvendorid
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2015-12-17 Scott Beameranother osx clang compatability fix
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-26 Andrew WatermanFix histogram for RVC
2015-09-16 Scott Beamercommit log now correctly prints privilege
2015-09-09 Andrew WatermanImprove instruction fetch
2015-07-05 Andrew WatermanNew machine-mode timer facility
2015-06-01 Andrew WatermanUse single, shared real-time counter
2015-06-01 Andrew WatermanTake interrupts as soon as interrupts are enabled
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-27 Andrew WatermanSerialize counters without throwing C++ exceptions
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-26 Andrew WatermanFix commit log
2014-12-01 Andrew WatermanImplement timer faithfully
2014-08-15 Christopher CelioAdded PC histogram option.
2014-06-13 Andrew WatermanOnly print commit log if instruction commits
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-03-15 Andrew Watermanspeed up compilation a bit
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-08-13 Andrew WatermanImplement RoCC and add a dummy RoCC
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermanexpose pending interrupts in status register
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-07-23 Andrew Watermancorrect HTIF reset behavior
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-03-20 Andrew Watermanabstract regfile behind object
2012-01-23 Andrew Watermandisentangle decode.h from other headers
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
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