Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / bus /
2022-05-23 Andrey MiroshnikovChange usage of WB sel for individual control
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc
2022-04-16 Luke Kenneth Casso... whoops, WBASyncBridge ack signal not wired up!
2022-04-16 Luke Kenneth Casso... select width is data_width // data granularity.
2022-04-14 Luke Kenneth Casso... move IRQLine out because that makes soc dependent on...
2022-04-14 Luke Kenneth Casso... 80 char limit, remove creation of stall from ack/cyc...
2022-04-14 Raptor Engineering... wb_async: Allow different feature fields for master...
2022-04-14 Raptor Engineering... Add separate memory clock register to SYSCON
2022-04-11 Raptor Engineering... Separate core and nest clocks in Microwatt SYSCON
2022-04-11 Raptor Engineering... Add initial wrapper for Wishbone asynchronous bridge...
2022-04-08 Luke Kenneth Casso... syntax error
2022-04-08 Luke Kenneth Casso... add dram to SysCon
2022-04-08 Luke Kenneth Casso... add SPI offset to microwatt syscon
2022-04-06 Luke Kenneth Casso... only add clock-settings on ECP5 due to special SPI...
2022-04-04 Luke Kenneth Casso... add tempfile to uart16550 wrapper which defines DATA_BU...
2022-04-04 Luke Kenneth Casso... allow direction-setting on each of dq0-3 in Tercel...
2022-04-03 Luke Kenneth Casso... fix some of instantiation errors in opencores_ethmac.py
2022-04-02 Raptor Engineering... Fix opencores EthMAC module wiring
2022-03-31 Luke Kenneth Casso... invert cs_n pin in Tercel
2022-03-30 Luke Kenneth Casso... nope, default features in Tercel WB Buses need to not...
2022-03-29 Luke Kenneth Casso... add bus.err to list of default Wishbone signals in...
2022-03-29 Luke Kenneth Casso... byte-reverse Tercel read/write data and config bus...
2022-03-29 Luke Kenneth Casso... set clock freq Constant length to 32-bit in Tercel.
2022-03-29 Luke Kenneth Casso... self.specials does not exist, Instances must be added...
2022-03-29 Luke Kenneth Casso... more sorting out wishbone names in Tercel
2022-03-29 Luke Kenneth Casso... fix names of Instance signals in Tercel
2022-03-29 Luke Kenneth Casso... sort out variable names in Tercel
2022-03-29 Luke Kenneth Casso... self.comb does not exist, comb is a local temp-var...
2022-03-29 Luke Kenneth Casso... whitespace cleanup (80 char limit)
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC
2022-03-18 Luke Kenneth Casso... whitespace cleanup (80 char limit, pep8)
2022-03-16 Raptor Engineering... Add initial Tercel integration
2022-03-08 Luke Kenneth Casso... work-in-progress on sdram opencores wrapper
2022-02-18 Luke Kenneth Casso... add SDRAM Configuration Record
2022-02-18 Luke Kenneth Casso... parameterise I-Cache similar to D-Cache. lots of "self."
2022-02-17 Luke Kenneth Casso... add opencores SDRAM verilog wrapper
2022-02-16 Luke Kenneth Casso... connect UART16550 pins if given
2022-02-15 Luke Kenneth Casso... for *write* the counter-address on downconvert was...
2022-02-15 Luke Kenneth Casso... add wishbone downconvert "skip" of slave sel so that...
2022-02-15 Luke Kenneth Casso... add SysCon reg_info, has uart and has large SYSCON
2022-02-15 Luke Kenneth Casso... sigh, stall was not working but actually turns out...
2022-02-15 Luke Kenneth Casso... add option to specify UART16550 width (32/8)
2022-02-15 Luke Kenneth Casso... add beginnings of syscon bus peripheral
2022-02-15 Luke Kenneth Casso... update comments
2022-02-15 Luke Kenneth Casso... resolve WBDownConvert ack issues when stall is active
2022-02-14 Luke Kenneth Casso... strip first 3 bits of WB address from microwatt d/i...
2022-02-14 Luke Kenneth Casso... slave sends stall signal, master receives, in
2022-02-14 Luke Kenneth Casso... sort out ExternalCore signal names
2022-02-14 Luke Kenneth Casso... add wishbone slave signal to downconvert if present
2022-02-14 Luke Kenneth Casso... add external core verilog wrapper, ironically around...
2022-02-13 Luke Kenneth Casso... bugfixing for ls2 imports of uart16550
2022-02-09 Luke Kenneth Casso... add opencores uart16550 instance wrapper
2021-05-27 Luke Kenneth Casso... corrections on spblock ack
2021-05-27 Luke Kenneth Casso... classic wishbone mode: must not do ack if already acked
2021-05-24 Luke Kenneth Casso... whoops sort out name of SPBlock RAM
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-04-30 Luke Kenneth Casso... sort out spblock 4k sram cell instance name to match...
2021-04-26 Luke Kenneth Casso... comment read ack in sram
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-20 Luke Kenneth Casso... add wishbone sram.py (move from nmigen-soc)
2021-04-19 Luke Kenneth Casso... give independent names to spblock512w64b8ws
2021-04-18 Luke Kenneth Casso... give spblock512 a name as a submodule
2021-04-18 Luke Kenneth Casso... rename SPBlock_512W64B8W to lowercase
2021-04-06 Luke Kenneth Casso... 4k SRAM Instance needs write-enable @ 8-bit width
2021-03-06 Luke Kenneth Casso... remove blackbox attribute on SPBlock_512W64B8W
2021-03-05 Luke Kenneth Casso... extend name of sram4k block with _wb suffix
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2021-02-20 Luke Kenneth Casso... add black-box attribute to 4k SRAM cell
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth Casso... add Wishbone-wrapped SPBlock_512W64B8W
2020-12-20 Cesar StraussAdd support for CXXSim simulation
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py
2020-09-05 Luke Kenneth Casso... move wb read/write to separate util test library and...
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-20 Luke Kenneth Casso... bugfix wishbone downconvert using wb sram 64-to-32...
2020-08-20 Luke Kenneth Casso... add a wishbone upconverter
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... whoops error in test of dynamic parameter
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in...
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct
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