riscv-isa-sim.git
8 years agoFix reading CSRs.
Tim Newsome [Thu, 5 May 2016 18:21:07 +0000 (11:21 -0700)]
Fix reading CSRs.

8 years agoSingle step appears to work.
Tim Newsome [Thu, 5 May 2016 01:51:26 +0000 (18:51 -0700)]
Single step appears to work.

8 years agoSoftware breakpoints sort of work.
Tim Newsome [Wed, 4 May 2016 20:14:46 +0000 (13:14 -0700)]
Software breakpoints sort of work.

8 years agoUse fence.i in Debug ROM.
Tim Newsome [Wed, 4 May 2016 16:45:56 +0000 (09:45 -0700)]
Use fence.i in Debug ROM.

This replaces a hack that just disabled all of the icache.

8 years agoFix off-by-two in general read registers.
Tim Newsome [Wed, 4 May 2016 16:40:20 +0000 (09:40 -0700)]
Fix off-by-two in general read registers.

Now the exit test passes!

8 years agoWalk page tables to translate addresses.
Tim Newsome [Wed, 4 May 2016 01:53:16 +0000 (18:53 -0700)]
Walk page tables to translate addresses.

8 years agoTurn operation into a queue,
Tim Newsome [Tue, 3 May 2016 20:46:57 +0000 (13:46 -0700)]
Turn operation into a queue,

in preparation for address translation.

8 years agoRemove unused code.
Tim Newsome [Tue, 3 May 2016 19:24:25 +0000 (12:24 -0700)]
Remove unused code.

Add some debug printfs, which I'll be wanting for at least a little
while.

8 years agoSave/restore mstatus, too.
Tim Newsome [Tue, 3 May 2016 17:55:00 +0000 (10:55 -0700)]
Save/restore mstatus, too.

Also read DCSR, which will be useful to figure out why we halted.

8 years agoIgnore more files.
Tim Newsome [Tue, 3 May 2016 17:54:08 +0000 (10:54 -0700)]
Ignore more files.

8 years agoProperly read s0/s1.
Tim Newsome [Tue, 3 May 2016 17:43:27 +0000 (10:43 -0700)]
Properly read s0/s1.

8 years agoAdd dret.
Tim Newsome [Tue, 3 May 2016 01:07:51 +0000 (18:07 -0700)]
Add dret.

8 years agoImplement memory writes.
Tim Newsome [Mon, 2 May 2016 22:04:03 +0000 (15:04 -0700)]
Implement memory writes.

8 years agoImplement single memory read access.
Tim Newsome [Sun, 1 May 2016 20:18:03 +0000 (13:18 -0700)]
Implement single memory read access.

Prevent unaligned accesses in memory read.

Also change how exceptions in Debug Mode are signaled.

8 years agoProperly save/restore dpc, mcause, mbadaddr.
Tim Newsome [Sun, 1 May 2016 16:53:23 +0000 (09:53 -0700)]
Properly save/restore dpc, mcause, mbadaddr.

Also clear dcsr.cause when leaving Debug Mode so future traps go where
they should.

8 years agoExceptions in Debug Mode, stay in Debug Mode.
Tim Newsome [Sat, 30 Apr 2016 22:24:38 +0000 (15:24 -0700)]
Exceptions in Debug Mode, stay in Debug Mode.

Now things don't blow up when reading a non-existent CSR.

8 years agoRemove debug printfs.
Tim Newsome [Sun, 1 May 2016 19:26:29 +0000 (12:26 -0700)]
Remove debug printfs.

8 years agoHave Debug memory kind of working again.
Tim Newsome [Sun, 1 May 2016 19:05:48 +0000 (12:05 -0700)]
Have Debug memory kind of working again.

Debug exception -> ROM -> RAM -> ROM, then something goes wrong.

8 years agoRead FP registers, and general CSRs*
Tim Newsome [Fri, 29 Apr 2016 20:38:59 +0000 (13:38 -0700)]
Read FP registers, and general CSRs*

*) Only works if you read CSRs that actually exist.

8 years agoContinue works well enough for DebugTest.test_exit
Tim Newsome [Fri, 29 Apr 2016 18:17:58 +0000 (11:17 -0700)]
Continue works well enough for DebugTest.test_exit

8 years agoFix race using fence.
Tim Newsome [Thu, 28 Apr 2016 20:15:46 +0000 (13:15 -0700)]
Fix race using fence.

8 years agoRefactor how we track in-progress operations.
Tim Newsome [Wed, 27 Apr 2016 20:52:54 +0000 (13:52 -0700)]
Refactor how we track in-progress operations.

I think the functionality is unchanged.

8 years agogdb can attach and read the PC:
Tim Newsome [Tue, 26 Apr 2016 21:32:08 +0000 (14:32 -0700)]
gdb can attach and read the PC:

(gdb) target remote localhost:1234
Remote debugging using localhost:1234
0x0000000000010178 in fib (n=0) at waste.c:1
1       unsigned int fib(unsigned int n) {
(gdb)

8 years agoprocessor_t unfriends gdbserver_t.
Tim Newsome [Tue, 26 Apr 2016 19:12:57 +0000 (12:12 -0700)]
processor_t unfriends gdbserver_t.

8 years agoCorrectly read PC on halt.
Tim Newsome [Tue, 26 Apr 2016 17:22:02 +0000 (10:22 -0700)]
Correctly read PC on halt.

8 years agoFix store to clear debug interrupt.
Tim Newsome [Tue, 26 Apr 2016 15:29:17 +0000 (08:29 -0700)]
Fix store to clear debug interrupt.

8 years agoAdd debug_module bus device.
Tim Newsome [Sun, 24 Apr 2016 15:54:19 +0000 (08:54 -0700)]
Add debug_module bus device.

This should replace the ROM hack I implemented earlier, but for now both
exist together.

Back to the point where gdb connects, core jumps to ROM->RAM->ROM.

8 years agoROM -> RAM -> ROM, waiting for debug int.
Tim Newsome [Sat, 23 Apr 2016 18:09:07 +0000 (11:09 -0700)]
ROM -> RAM -> ROM, waiting for debug int.

8 years agoMake sure to translate Debug RAM addresses also.
Tim Newsome [Sat, 23 Apr 2016 17:40:23 +0000 (10:40 -0700)]
Make sure to translate Debug RAM addresses also.

8 years agoJump to the correct (temporary) Debug RAM address.
Tim Newsome [Sat, 23 Apr 2016 17:25:57 +0000 (10:25 -0700)]
Jump to the correct (temporary) Debug RAM address.

8 years agoClean up how Debug ROM is included.
Tim Newsome [Sat, 23 Apr 2016 17:18:05 +0000 (10:18 -0700)]
Clean up how Debug ROM is included.

I'm not thrilled about including a static copy in so many cc files, and
making the compiler throw it out. But without really grokking the
Makefile this is the best it's going to be.

8 years agoCan jump to and execute Debug ROM.
Tim Newsome [Sat, 23 Apr 2016 03:11:29 +0000 (20:11 -0700)]
Can jump to and execute Debug ROM.

Connect with gdb, and the core will jump to Debug ROM and start
executing it. Then it crashes when it jumps to 0x400 because Debug RAM
isn't implemented (and doesn't live there anyway, for now).

8 years agoCheck in compiled debug ROM.
Tim Newsome [Fri, 22 Apr 2016 22:11:26 +0000 (15:11 -0700)]
Check in compiled debug ROM.

Not everybody will have a cross-compiled toolchain set up when they
build spike.

8 years agoWhen gdb connects, jump to Debug ROM and segfault.
Tim Newsome [Fri, 22 Apr 2016 22:10:23 +0000 (15:10 -0700)]
When gdb connects, jump to Debug ROM and segfault.

8 years agoAdd debug rom code.
Tim Newsome [Fri, 22 Apr 2016 22:08:35 +0000 (15:08 -0700)]
Add debug rom code.

8 years agoGutting direct-access gdb.
Tim Newsome [Fri, 22 Apr 2016 19:09:59 +0000 (12:09 -0700)]
Gutting direct-access gdb.

8 years agoAdd writing to DCSR, DPC, DSCRATCH.
Tim Newsome [Thu, 21 Apr 2016 22:53:46 +0000 (15:53 -0700)]
Add writing to DCSR, DPC, DSCRATCH.

Make those 3 CSRs writable.

8 years agoActually run the ebreak test.
Tim Newsome [Wed, 30 Mar 2016 17:43:45 +0000 (10:43 -0700)]
Actually run the ebreak test.

8 years agoOnly halt on ebreak if a debugger is attached.
Tim Newsome [Thu, 24 Mar 2016 00:42:17 +0000 (17:42 -0700)]
Only halt on ebreak if a debugger is attached.

8 years agoTest ebreak without gdb.
Tim Newsome [Wed, 23 Mar 2016 23:14:50 +0000 (16:14 -0700)]
Test ebreak without gdb.

Currently this test fails.

8 years agoDocument attaching with gdb.
Tim Newsome [Sat, 19 Mar 2016 20:39:41 +0000 (13:39 -0700)]
Document attaching with gdb.

8 years agoAdd --gdb-port
Tim Newsome [Sat, 19 Mar 2016 20:33:58 +0000 (13:33 -0700)]
Add --gdb-port

It's necessary to be able to run multiple spikes at once on the same
box.

8 years agoDo a better job checking CSR functionality.
Tim Newsome [Thu, 17 Mar 2016 19:51:58 +0000 (12:51 -0700)]
Do a better job checking CSR functionality.

8 years agoRename gdbserver-smoke.py to gdbserver.py.
Tim Newsome [Wed, 16 Mar 2016 18:07:50 +0000 (11:07 -0700)]
Rename gdbserver-smoke.py to gdbserver.py.

It's not really a smoketest anymore.

8 years agoTest 'info registers all' as well as 'info all-registers'
Tim Newsome [Wed, 16 Mar 2016 18:02:52 +0000 (11:02 -0700)]
Test 'info registers all' as well as 'info all-registers'

8 years agoMinor cleanup.
Tim Newsome [Tue, 15 Mar 2016 23:15:53 +0000 (16:15 -0700)]
Minor cleanup.

8 years agoUpdate regnum handling to match gdb CSR changes.
Tim Newsome [Tue, 15 Mar 2016 20:50:17 +0000 (13:50 -0700)]
Update regnum handling to match gdb CSR changes.

8 years agoForgot to add this source.
Tim Newsome [Mon, 14 Mar 2016 20:39:47 +0000 (13:39 -0700)]
Forgot to add this source.

8 years agoTreat warnings as errors.
Tim Newsome [Mon, 14 Mar 2016 20:29:53 +0000 (13:29 -0700)]
Treat warnings as errors.

The code compiles cleanly right now. Let's keep it that way.

8 years agoImplement register writes.
Tim Newsome [Mon, 14 Mar 2016 18:54:29 +0000 (11:54 -0700)]
Implement register writes.

8 years agoProperly clean up spike.
Tim Newsome [Sun, 13 Mar 2016 23:23:59 +0000 (16:23 -0700)]
Properly clean up spike.

8 years agoImplement reading of CSRs.
Tim Newsome [Sun, 13 Mar 2016 22:39:08 +0000 (15:39 -0700)]
Implement reading of CSRs.

8 years agoAdd some tests that pass and test something.
Tim Newsome [Sun, 13 Mar 2016 20:13:15 +0000 (13:13 -0700)]
Add some tests that pass and test something.

8 years agoFlush icache when using swbps and report to gdb.
Tim Newsome [Sun, 13 Mar 2016 01:50:32 +0000 (17:50 -0800)]
Flush icache when using swbps and report to gdb.

8 years agoAdd very basic 'make check'.
Tim Newsome [Fri, 11 Mar 2016 02:14:31 +0000 (18:14 -0800)]
Add very basic 'make check'.

The existing stuff all assumes you're writing your tests in C++.

8 years agoMake 'make check' not hang forever.
Tim Newsome [Fri, 11 Mar 2016 01:57:23 +0000 (17:57 -0800)]
Make 'make check' not hang forever.

8 years agoSoftware breakpoints seem to work.
Tim Newsome [Thu, 10 Mar 2016 20:29:29 +0000 (12:29 -0800)]
Software breakpoints seem to work.

8 years agoRewrite GPL'd code from OpenOCD.
Tim Newsome [Thu, 10 Mar 2016 18:04:04 +0000 (10:04 -0800)]
Rewrite GPL'd code from OpenOCD.

8 years agoLooks like single step works.
Tim Newsome [Thu, 10 Mar 2016 02:48:20 +0000 (18:48 -0800)]
Looks like single step works.

8 years agoAdd -H to start halted.
Tim Newsome [Thu, 10 Mar 2016 01:16:26 +0000 (17:16 -0800)]
Add -H to start halted.

8 years agoImplement binary memory write.
Tim Newsome [Wed, 9 Mar 2016 18:31:51 +0000 (10:31 -0800)]
Implement binary memory write.

Also set the simulation running again when gdb disconnects.

8 years agoNow you can halt/continue from gdb.
Tim Newsome [Wed, 9 Mar 2016 05:56:31 +0000 (21:56 -0800)]
Now you can halt/continue from gdb.

8 years agoRegister read looks sane now.
Tim Newsome [Wed, 9 Mar 2016 05:13:55 +0000 (21:13 -0800)]
Register read looks sane now.

8 years agogdb can now read spike memory.
Tim Newsome [Mon, 7 Mar 2016 23:44:20 +0000 (15:44 -0800)]
gdb can now read spike memory.

The endianness is wrong, but I think it might be that gdb doesn't have
it right. Need to investigate what architecture gdb thinks it's
debugging.

8 years agoHack to the point where gdb reads a register.
Tim Newsome [Mon, 7 Mar 2016 04:59:26 +0000 (20:59 -0800)]
Hack to the point where gdb reads a register.

8 years agoListen on a socket for gdb to connect to.
Tim Newsome [Sun, 6 Mar 2016 01:35:06 +0000 (17:35 -0800)]
Listen on a socket for gdb to connect to.

So far it just listens, and gdb times out because it's not getting any
messages back.

Receive packets and verify their checksum.

8 years agoAllow delegation of device interrupts
Andrew Waterman [Sun, 22 May 2016 09:35:33 +0000 (02:35 -0700)]
Allow delegation of device interrupts

8 years agohtif: catch proper store exception (#44)
Garret Kelly [Sat, 21 May 2016 22:41:28 +0000 (18:41 -0400)]
htif: catch proper store exception (#44)

The sim's debug_mmu will generate a trap_load_access_fault if the load
fails, not a trap_store_access_fault.  This doesn't materially affect
exection, but results in a nicer log message.

8 years agoSome bugfixes for CSR reading and setting FS for fflags updates (#43)
Andy Wright [Sat, 21 May 2016 20:39:21 +0000 (16:39 -0400)]
Some bugfixes for CSR reading and setting FS for fflags updates (#43)

* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0

* Dirty fp state when setting new fp exceptions

* Set FS to dirty for all non-zero fflags writes.

8 years agoMerge pull request #42 from csail-csg/master
Tim Newsome [Thu, 19 May 2016 23:34:21 +0000 (16:34 -0700)]
Merge pull request #42 from csail-csg/master

Removed devicetree.h from riscv.mk.in since it no longer exists

8 years agoRemoved devicetree.h from riscv.mk.in since it no longer exists
acw1251 [Thu, 19 May 2016 20:17:57 +0000 (16:17 -0400)]
Removed devicetree.h from riscv.mk.in since it no longer exists

8 years agoAdded missing header files to riscv.mk.in
acw1251 [Mon, 16 May 2016 19:39:37 +0000 (15:39 -0400)]
Added missing header files to riscv.mk.in

Merges #40

8 years agoAdd back IPI support
Andrew Waterman [Mon, 2 May 2016 23:28:51 +0000 (16:28 -0700)]
Add back IPI support

8 years agoRemove MIPI; mip.MSIP bit is read-only
Andrew Waterman [Mon, 2 May 2016 22:11:25 +0000 (15:11 -0700)]
Remove MIPI; mip.MSIP bit is read-only

8 years agoRemove tohost/fromhost registers
Andrew Waterman [Mon, 2 May 2016 21:13:52 +0000 (14:13 -0700)]
Remove tohost/fromhost registers

8 years agoInitialize mtvec to DEFAULT_MTVEC
Andrew Waterman [Sun, 1 May 2016 03:43:00 +0000 (20:43 -0700)]
Initialize mtvec to DEFAULT_MTVEC

8 years agoRemove SCRs; add padding after config string
Andrew Waterman [Sun, 1 May 2016 00:48:07 +0000 (17:48 -0700)]
Remove SCRs; add padding after config string

8 years agoMove much closer to new platform-M memory map
Andrew Waterman [Fri, 29 Apr 2016 20:48:56 +0000 (13:48 -0700)]
Move much closer to new platform-M memory map

Reset vector is at 0x1000; below that is reserved for debug
Memory is at 0x80000000

8 years agoAdd --dump-config-string flag
Andrew Waterman [Thu, 28 Apr 2016 22:17:28 +0000 (15:17 -0700)]
Add --dump-config-string flag

8 years agoRemove MTIME[CMP]; add RTC device
Andrew Waterman [Thu, 28 Apr 2016 22:01:09 +0000 (15:01 -0700)]
Remove MTIME[CMP]; add RTC device

8 years agoSplit ERET into URET, SRET, HRET, MRET
Andrew Waterman [Wed, 20 Apr 2016 00:31:54 +0000 (17:31 -0700)]
Split ERET into URET, SRET, HRET, MRET

8 years agoRemove non-standard uarch CSRs
Andrew Waterman [Wed, 6 Apr 2016 17:20:24 +0000 (10:20 -0700)]
Remove non-standard uarch CSRs

8 years agoAllow configuration of default ISA with --with-isa
Andrew Waterman [Sun, 3 Apr 2016 00:32:23 +0000 (17:32 -0700)]
Allow configuration of default ISA with --with-isa

8 years agoUpdate definition of base field in misa register
Andrew Waterman [Thu, 17 Mar 2016 06:43:33 +0000 (23:43 -0700)]
Update definition of base field in misa register

8 years agoFix up interrupt delegation
Andrew Waterman [Fri, 4 Mar 2016 01:01:48 +0000 (17:01 -0800)]
Fix up interrupt delegation

8 years agoAdd counter-enable registers
Andrew Waterman [Tue, 1 Mar 2016 23:03:00 +0000 (15:03 -0800)]
Add counter-enable registers

8 years agoUse RV config string rather than FDT
Andrew Waterman [Tue, 1 Mar 2016 23:01:29 +0000 (15:01 -0800)]
Use RV config string rather than FDT

8 years agoWIP on priv spec v1.9
Andrew Waterman [Mon, 29 Feb 2016 07:51:53 +0000 (23:51 -0800)]
WIP on priv spec v1.9

8 years agoNew definitions of misa/marchid/mvendorid
Andrew Waterman [Mon, 29 Feb 2016 04:40:11 +0000 (20:40 -0800)]
New definitions of misa/marchid/mvendorid

8 years agoimplement PUM functionality
Andrew Waterman [Fri, 19 Feb 2016 21:06:57 +0000 (13:06 -0800)]
implement PUM functionality

8 years agosptbr now a holds a PPN, not an address
Andrew Waterman [Fri, 19 Feb 2016 21:05:50 +0000 (13:05 -0800)]
sptbr now a holds a PPN, not an address

8 years agoReturn to interactive mode after a trap
Andrew Waterman [Fri, 12 Feb 2016 18:59:46 +0000 (10:59 -0800)]
Return to interactive mode after a trap

8 years agoUse simpler MTVEC scheme
Andrew Waterman [Fri, 12 Feb 2016 18:59:34 +0000 (10:59 -0800)]
Use simpler MTVEC scheme

8 years agoFix ERET bug
Andrew Waterman [Fri, 12 Feb 2016 18:58:43 +0000 (10:58 -0800)]
Fix ERET bug

8 years agoZero-extend all CSR writes
Andrew Waterman [Tue, 9 Feb 2016 22:26:06 +0000 (14:26 -0800)]
Zero-extend all CSR writes

This fixes an RV32 HTIF issue.

8 years agoFix ERET serialization strategy
Andrew Waterman [Tue, 9 Feb 2016 07:29:41 +0000 (23:29 -0800)]
Fix ERET serialization strategy

It was screwing up the commit log.

8 years agoAdd autoconf check for little-endianness
Andrew Waterman [Mon, 8 Feb 2016 01:24:59 +0000 (17:24 -0800)]
Add autoconf check for little-endianness

8 years agoSet default RV32 RAM size to 4 GiB - 256 MiB
Andrew Waterman [Mon, 8 Feb 2016 01:05:21 +0000 (17:05 -0800)]
Set default RV32 RAM size to 4 GiB - 256 MiB

This allows, by default, 256 MiB of addressable I/O space.

8 years agoSerialize simulator on ERET
Andrew Waterman [Mon, 8 Feb 2016 01:04:28 +0000 (17:04 -0800)]
Serialize simulator on ERET

This guarantees interrupts will eventually be taken.

8 years agoWIP on priv spec v1.9
Andrew Waterman [Sat, 6 Feb 2016 02:18:06 +0000 (18:18 -0800)]
WIP on priv spec v1.9