Zero-extend flw, fmv_s_x instructions
[riscv-isa-sim.git] / riscv /
2015-09-15 Christopher CelioZero-extend flw, fmv_s_x instructions
2015-09-12 Scott Beamerprint out current privilege level (if commit log enabled)
2015-09-12 Scott Beamerprint out commit log (if enabled) for all privilege...
2015-09-11 Andrew WatermanSimplify register_base_instructions
2015-09-11 Andrew WatermanInitialize mstatus.prv1/prv2 to U, not S
2015-09-11 Andrew WatermanSupport 'G' in ISA strings
2015-09-11 Andrew WatermanMerge pull request #32 from riscv/insn-list
2015-09-11 Albert OuFix non-portable sed commands generating insn_list.h
2015-09-09 Andrew WatermanImprove instruction fetch
2015-09-08 Andrew WatermanAdd facility to instrument specific opcodes
2015-09-08 Andrew WatermanRefer to LICENSE in some newer source files
2015-09-04 Andrew WatermanMove towards RVC v1.8
2015-09-02 Andrew WatermanDon't automatically run autoconf
2015-08-06 Andrew WatermanMerge pull request #29 from pmundkur/devel
2015-08-06 Prashanth MundkurAdd an option (-l) to display a log of execution in...
2015-07-30 Christopher CelioAdded error message when trying to use histogram
2015-07-15 Andrew WatermanMerge pull request #28 from sbeamer/master
2015-07-13 Scott Beamersimplified default case and added comments
2015-07-11 Andrew WatermanMerge pull request #27 from sbeamer/master
2015-07-11 Scott Beamerfix clang compile error
2015-07-05 Andrew WatermanNew machine-mode timer facility
2015-06-06 Andrew WatermanMerge pull request #25 from vapier/master
2015-06-05 Mike Frysingerallow interactive "reg" command to dump all registers
2015-06-05 Mike Frysingeradd an interactive "pc" command
2015-06-05 Mike Frysingerunify interactive core processing
2015-06-04 Andrew WatermanMerge pull request #24 from vapier/master
2015-06-04 Mike Frysingeradd aliases for common interactive functions
2015-06-04 Mike Frysingeradd a help screen to interactive mode
2015-06-03 Andrew WatermanMerge pull request #23 from vapier/master
2015-06-03 Mike Frysingermove interactive function init out of main loop
2015-06-01 Andrew WatermanUse single, shared real-time counter
2015-06-01 Andrew WatermanExecute exactly the # of insns passed to step()
2015-06-01 Andrew WatermanAdd rest of RV32C instructions
2015-06-01 Andrew WatermanFix performance bug when CSR accesses are common
2015-06-01 Andrew WatermanFix c.slliw implementation
2015-06-01 Andrew WatermanNew RV64C proposal
2015-06-01 Andrew WatermanTake interrupts as soon as interrupts are enabled
2015-05-15 Andrew WatermanMerge pull request #20 from palmer-dabbelt/package
2015-05-14 Andrew WatermanFix VM, MIP encoding
2015-05-13 Palmer DabbeltInstall "disasm.h"
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-30 Andrew WatermanFix commit log for CSR instructions
2015-04-26 Andrew WatermanFix I$ simulator hit count
2015-04-14 Andrew WatermanMerge pull request #18 from wsong83/master
2015-04-13 Wei Songfix cache line index offset in cachesim.cc
2015-04-04 Andrew WatermanCheck for F extension when accessing FCSR
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-04-02 Andrew WatermanSimplify RV32 comparisons
2015-03-31 Andrew WatermanAllow writing mstatus.fs even if FPU isn't present
2015-03-31 Andrew WatermanImplement RVC draft
2015-03-27 Andrew WatermanSerialize counters without throwing C++ exceptions
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-26 Andrew WatermanUpdate state.pc on every instruction
2015-03-21 Andrew WatermanFor misaligned fetch, set mepc = addr of branch/jump
2015-03-17 Yunsup Leebugfix, mbadaddr should be writable
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-16 Yunsup Leebugfix in raising accelerator interrupts
2015-03-14 Andrew WatermanDon't set dirty/referenced bits w/o permission
2015-03-13 Andrew WatermanUse hcall instead of mcall
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-02-08 Andrew WatermanUse xlen, not xprlen, to refer to x-register width
2015-01-27 Christopher CelioFixed masking/casting logic in commit log printf.
2015-01-26 Andrew WatermanFix commit log
2015-01-09 Stephen TwiggFix bug where C compiler used instead of C++ for autoco...
2015-01-03 Andrew WatermanRequire 4-byte instruction alignment until RVC is reimp...
2015-01-03 Andrew WatermanOn misaligned fetch, set EPC to target, not branch...
2015-01-02 Andrew WatermanReduce dependences on auto-generated code
2014-12-05 Andrew WatermanSupport 2/4/6/8-byte instructions
2014-12-05 Andrew WatermanSet badvaddr on instruction page faults
2014-12-03 Andrew WatermanUpdate register names to match new ABI
2014-12-01 Andrew WatermanImplement timer faithfully
2014-11-25 Andrew WatermanFactor out the dummy RoCC accelerator
2014-11-22 Yunsup LeeRevert "Enable support for the four custom instructions"
2014-11-20 Andrew WatermanAdd missing makefile dependence
2014-11-07 Andrew WatermanMerge pull request #8 from arunthomas/dummy_rocc_test
2014-10-30 Arun Thomasdummy-rocc-test build fix
2014-10-24 Yunsup LeeMerge pull request #4 from arunthomas/custom_inst
2014-10-23 Arun ThomasEnable support for the four custom instructions
2014-09-27 Andrew WatermanAvoid some unused variable warnings
2014-09-27 Andrew WatermanAvoid use of __int128_t
2014-09-21 Scott BeamerMerge pull request #2 from arunthomas/build_fix
2014-09-21 Arun ThomasUpdate riscv.ac to set CPPFLAGS with fesvr include...
2014-08-26 Scott Beamerclean up warnings from clang
2014-08-15 Christopher CelioAdded PC histogram option.
2014-08-08 Andrew WatermanSupport uarch counters (degenerately)
2014-07-25 Scott Beameradded support for register convention names in debug...
2014-07-08 Andrew WatermanDisallow access to FCSR when FP is disabled
2014-07-07 Andrew WatermanUse precompiled headers to speed up compilation
2014-07-07 Andrew WatermanMinor refactoring
2014-06-13 Christopher CelioCommit log now prints while interrupts are enabled.
2014-06-13 Andrew WatermanOnly print commit log if instruction commits
2014-06-12 Andrew WatermanSet status.u64 to true on boot
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-04-03 Stephen TwiggSync encoding in opcodes
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-15 Andrew Watermanspeed up compilation a bit
2014-03-12 Andrew WatermanNew FP encoding
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-25 Yunsup Leeadd extensions to riscv-dis for better disassembly
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