| 2022-01-14 |
Luke Kenneth Casson... | missed setting r1.store_way and r1.store_row in STORE_WAIT_A...
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | Revert "dcache 2nd stage (r1) should only indicate...
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | second test for linux-5.7
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | add allow-overlap option to issuer_verilog.py
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | dcache 2nd stage (r1) should only indicate not-busy
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with priv_mode not being passed correctly...
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with d_valid in dcache, was not being set...
|
commit | commitdiff | tree |
| 2022-01-10 |
Luke Kenneth Casson... | LoadStore1 priv_mode was not being correctly picked...
|
commit | commitdiff | tree |
| 2022-01-09 |
Luke Kenneth Casson... | grab the LDST request address for microwatt verilator...
|
commit | commitdiff | tree |
| 2022-01-09 |
Luke Kenneth Casson... | add linux-5.7 unit test which showed a silly error:
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | fix MMU lookup after 2nd request (misaligned) by also...
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | add microwatt mmu.bin test5 to show page-fault on misaligned LD
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | do not clear out ldst request after TLB entry is added
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | enable microwatt mmu test2
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | whitespace and use exc is None not exc == None
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | add a second LD request to dcache which is merged with...
|
commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | start adding in mis-aligned LD/ST support into LoadStore1
|
commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add missing MSRSpec import
|
commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add msr_o to issuer in microwatt_compat mode
|
commit | commitdiff | tree |
| 2022-01-06 |
Luke Kenneth Casson... | double the number of lines in the L1 D/I-Cache to match...
|
commit | commitdiff | tree |
| 2022-01-06 |
Luke Kenneth Casson... | add SECOND_REQ state to loadstore.py, not yet implemented
|
commit | commitdiff | tree |
| 2022-01-05 |
Luke Kenneth Casson... | add easy-to-access debug reporting of instruction and PC
|
commit | commitdiff | tree |
| 2022-01-05 |
Luke Kenneth Casson... | use microwatt-specific PLRU due to bug in nmutil version
|
commit | commitdiff | tree |
| 2022-01-04 |
Luke Kenneth Casson... | fix DriverConflict over MSR write in Issuer/Core by...
|
commit | commitdiff | tree |
| 2022-01-04 |
Luke Kenneth Casson... | remove FetchFSM from TestIssuer (it served its purpose...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | doh, bus-hack was the wrong way round. *output* the...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | sigh, microwatts wishbone bus usage is non-wishbone...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | sigh have to allow external clocks and reset mess even...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | give module appropriate top-level name in microwatt...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | add missing ext_irq signal to testissuer in microwatt...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | adding an extra option to issuer_verilog.py to be able...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | bring external irq out for microwatt-compatible mode...
|
commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | stop display of LDSTCompUnit debug info on every cycle
|
commit | commitdiff | tree |
| 2021-12-30 |
Luke Kenneth Casson... | rename nia to cia in MMU input record and mmu FSM
|
commit | commitdiff | tree |
| 2021-12-28 |
Luke Kenneth Casson... | add misaligned mmu.bin test 5 notes: currently LoadStore1...
|
commit | commitdiff | tree |
| 2021-12-27 |
Luke Kenneth Casson... | found bug in mmu with calculating addrsh, should have...
|
commit | commitdiff | tree |
| 2021-12-27 |
Luke Kenneth Casson... | add mmu.py microwatt mmu.bin test4 page table
|
commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | good grief, finally tracked down a piece of missing...
|
commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | whoops, using variable RegStage0 in dcache stage_0...
|
commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | missed reset of d_valid in dcache.py and missed that its
|
commit | commitdiff | tree |
| 2021-12-26 |
Luke Kenneth Casson... | rename addr to raddr in LoadStore1 to avoid conflict...
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | add mmu.bin test2 to much simpler test_loadstore1.py
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | move msr in test_loadstore1.py outside of conditional...
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | move microwatt mmu.bin test 3 page table to test pagetables...
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | wait for MMU "done" when setting PRTBL and PIDR
|
commit | commitdiff | tree |
| 2021-12-25 |
Luke Kenneth Casson... | add microwatt mmu.bin regression test test_mmu_3
|
commit | commitdiff | tree |
| 2021-12-24 |
Luke Kenneth Casson... | enable instruction redirect in mmu ifetch test
|
commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | somehow managed to miss out setting r1.forward_valid1...
|
commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | uniquify names in dcache.py
|
commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | allow MSR reset to default to a value set by issuer_verilog.py
|
commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | pass in msr_reset to issuer_verilog.py
|
commit | commitdiff | tree |
| 2021-12-23 |
Luke Kenneth Casson... | add ability to set the reset values of RegFileArray
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | only use a single variable for ack adjusting in dcache.py
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | fix issues with running core in DMI "stopped" status...
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | when setting DSISR in LoadStore1 use correct load bit...
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | use correct X-Form L field in OP_MTMSRD
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | check problem state in OP_MTMSRD from original reg...
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops, use MSR.IR for I-Cache fetch!
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove unneeded state in LoadStore1
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on exception WAIT_MMU ACK in...
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear out instr_fault when exception is thrown
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | clear instruction fault on idle/valid in Loadstore1
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | ooo far too late at night to be doing this
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | whoops use C not Const
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | remove bus_ack (found bug in Simulation, sorted)
|
commit | commitdiff | tree |
| 2021-12-22 |
Luke Kenneth Casson... | bug in mmu setting radix tree size with one extra bit
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | continue to assert PC in FetchFSM if needed
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | enable I-Cache wishbone memory type in issuer_verilog...
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | whoops issuer_verilog.py enabling mmu has to pass microwatt_mmu
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | for each unit test case in test_issuer_mmu_data_path...
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | test_issuer_mmu_data_path.py needs to use wb_get because of
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu code-comments
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | use prtbl in proc_tbl_wait in mmu
|
commit | commitdiff | tree |
| 2021-12-21 |
Luke Kenneth Casson... | mmu.py comments
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | set up DAR correctly in unit tests, added set_ldst_spr...
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | unit tests for SPRs when MMU enabled,
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | code-comments in MMU
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | prefer not to invert when doing if/else.
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | more code-comments
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add RTPDE - Radit Tree Page Directory Entry - Record...
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | add (and ues) PRTBL Record in MMU
|
commit | commitdiff | tree |
| 2021-12-20 |
Luke Kenneth Casson... | create PGTBL Record and use it in MMU page_table_idle
|
commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add hard stop address in ifetch unit test, bit of a...
|
commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | set terminate if core terminate requested
|
commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | code-comments
|
commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | add DMI STOPADDR register and use it in HDLRunner to...
|
commit | commitdiff | tree |
| 2021-12-19 |
Luke Kenneth Casson... | break out when core is stopped in HDLRunner
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add link to XICS bugreport
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | sort out reset signalling after tracking down Simulation...
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | add icache/dcache/mmu unit test for TestIssuer
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | get instructions to re-run in issuer after I-Cache...
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | forgot to connect up I-Cache to MMU
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | move connection of bus.stall in icache.py,
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tidyup
|
commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tlb_req_index is TLB_BITS long not TLB_SIZE
|
commit | commitdiff | tree |
| next |
projects / soc.git / search