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Implement and test a "phased write port" memory
[soc.git] / src /
2022-04-02 Cesar StraussImplement and test a "phased write port" memory tree | commitdiff
2022-03-31 Luke Kenneth Casso... invert cs_n pin in Tercel tree | commitdiff
2022-03-30 Luke Kenneth Casso... nope, default features in Tercel WB Buses need to not... tree | commitdiff
2022-03-29 Luke Kenneth Casso... add bus.err to list of default Wishbone signals in... tree | commitdiff
2022-03-29 Luke Kenneth Casso... byte-reverse Tercel read/write data and config bus... tree | commitdiff
2022-03-29 Luke Kenneth Casso... set clock freq Constant length to 32-bit in Tercel. tree | commitdiff
2022-03-29 Luke Kenneth Casso... self.specials does not exist, Instances must be added... tree | commitdiff
2022-03-29 Luke Kenneth Casso... more sorting out wishbone names in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... fix names of Instance signals in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... sort out variable names in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... self.comb does not exist, comb is a local temp-var... tree | commitdiff
2022-03-29 Luke Kenneth Casso... whitespace cleanup (80 char limit) tree | commitdiff
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC tree | commitdiff
2022-03-27 Cesar StraussFinish the SRAM formal proof by implementing induction tree | commitdiff
2022-03-26 Cesar StraussAdd formal verification of the single port memory block tree | commitdiff
2022-03-26 Luke Kenneth Casso... rename PLRU modules to avoid conflict in microwatt tree | commitdiff
2022-03-18 Luke Kenneth Casso... whitespace cleanup (80 char limit, pep8) tree | commitdiff
2022-03-18 Luke Kenneth Casso... turn CompALU/CompLDST latches synchronous tree | commitdiff
2022-03-16 Raptor Engineering... Add initial Tercel integration tree | commitdiff
2022-03-13 Cesar StraussSimulate some read/write/modify operations on the SRAM... tree | commitdiff
2022-03-13 Cesar StraussAdd a Single R/W Port SRAM model tree | commitdiff
2022-03-12 Luke Kenneth Casso... add extra pipeline stages to ALU FU to make timing tree | commitdiff
2022-03-12 Luke Kenneth Casso... introduce extra register of delay to split combinatoria... tree | commitdiff
2022-03-12 Luke Kenneth Casso... Revert "read last row from r.wb.adr not r.req_adr in... tree | commitdiff
2022-03-12 Luke Kenneth Casso... Revert "store cur_state.pc+4 in separate register to... tree | commitdiff
2022-03-12 Luke Kenneth Casso... store cur_state.pc+4 in separate register to help reduce tree | commitdiff
2022-03-12 Luke Kenneth Casso... read last row from r.wb.adr not r.req_adr in icache tree | commitdiff
2022-03-08 Luke Kenneth Casso... remove stbs_done in icache.py tree | commitdiff
2022-03-08 Luke Kenneth Casso... remove ld_stbs_done from dcache: not needed tree | commitdiff
2022-03-08 Luke Kenneth Casso... work-in-progress on sdram opencores wrapper tree | commitdiff
2022-03-06 Cesar StraussCopy the startup delay from issuer.py to inorder.py tree | commitdiff
2022-02-28 Luke Kenneth Casso... attempting to introduce an extra few clock cycles delay... tree | commitdiff
2022-02-27 Luke Kenneth Casso... for lulz make I-Cache possible to set to 32-bit (XLEN=32) tree | commitdiff
2022-02-27 Luke Kenneth Casso... bit_length is 1 more than needed: subtract 1 from XLEN... tree | commitdiff
2022-02-27 Luke Kenneth Casso... fix up shift_rot test_pipe_caller to new regspeckls... tree | commitdiff
2022-02-27 Luke Kenneth Casso... convert shift_rot pipeline to XLEN=32/64 tree | commitdiff
2022-02-27 Luke Kenneth Casso... fix up Logical pipeline to produce HDL with XLEN=32 tree | commitdiff
2022-02-27 Luke Kenneth Casso... whoops ALU common output target must be XLEN-bit, tree | commitdiff
2022-02-27 Luke Kenneth Casso... set up dummy parent_pspec to pass XLEN=64 in tree | commitdiff
2022-02-27 Luke Kenneth Casso... start on converting MUL and DIV pipelines to XLEN tree | commitdiff
2022-02-27 Luke Kenneth Casso... convert from public static functions/properties for... tree | commitdiff
2022-02-27 Luke Kenneth Casso... fix ALU with XLEN=32, carry and overflow tree | commitdiff
2022-02-27 Luke Kenneth Casso... use XLEN in Function Units (starting with ALU) tree | commitdiff
2022-02-27 Luke Kenneth Casso... add XLEN to issuer_verilog.py defaults to 64 tree | commitdiff
2022-02-27 Luke Kenneth Casso... add XLEN option to regfiles via pspec tree | commitdiff
2022-02-24 Jacob Lifshayadd running instructions tree | commitdiff
2022-02-24 Jacob Lifshayadd formal proof for shift/rot o.ok tree | commitdiff
2022-02-24 Jacob Lifshayclean up code tree | commitdiff
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCR tree | commitdiff
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCL tree | commitdiff
2022-02-24 Jacob Lifshayadd formal proof for OP_RLC tree | commitdiff
2022-02-23 Luke Kenneth Casso... forgot to pass cix (cache-inhibited) through to LD... tree | commitdiff
2022-02-22 Jacob Lifshayspeed up shift/rot formal proof by running stuff in... tree | commitdiff
2022-02-21 Luke Kenneth Casso... again reduce combinatorial chains, similar to Trap... tree | commitdiff
2022-02-20 Luke Kenneth Casso... add syn_ramstyle "block_ram" attributes and reduce... tree | commitdiff
2022-02-20 Luke Kenneth Casso... same as shiftrot, split out separate pipelines for... tree | commitdiff
2022-02-20 Luke Kenneth Casso... put LDST go-store on a 1-clock delay to help with combi... tree | commitdiff
2022-02-20 Luke Kenneth Casso... name core_stop and terminated_o synchronous to potentia... tree | commitdiff
2022-02-20 Luke Kenneth Casso... nope, it's perfectly fine tree | commitdiff
2022-02-20 Luke Kenneth Casso... weird exception, oe not found in the shiftrot input... tree | commitdiff
2022-02-20 Luke Kenneth Casso... separate out shiftrot stages due to size of main stage... tree | commitdiff
2022-02-18 Luke Kenneth Casso... add blockram style to regfile Memory tree | commitdiff
2022-02-18 Luke Kenneth Casso... use block_ram attribute for FPGA synthesis tree | commitdiff
2022-02-18 Luke Kenneth Casso... reduce number of d-cache lines in microwatt fpga mode tree | commitdiff
2022-02-18 Luke Kenneth Casso... couple of adjustments to reduce gate count in i/d-cache tree | commitdiff
2022-02-18 Luke Kenneth Casso... add SDRAM Configuration Record tree | commitdiff
2022-02-18 Luke Kenneth Casso... reduce TLB set size from 64 to 16 to get FPGA resource... tree | commitdiff
2022-02-18 Luke Kenneth Casso... drastically reduce I-Cache size in microwatt-compat... tree | commitdiff
2022-02-18 Luke Kenneth Casso... parameterise I-Cache similar to D-Cache. lots of "self." tree | commitdiff
2022-02-18 Jacob Lifshayadd grev tree | commitdiff
2022-02-17 Luke Kenneth Casso... add opencores SDRAM verilog wrapper tree | commitdiff
2022-02-16 Luke Kenneth Casso... oof. big update to DCache to accept config parameters tree | commitdiff
2022-02-16 Luke Kenneth Casso... connect UART16550 pins if given tree | commitdiff
2022-02-15 Luke Kenneth Casso... for *write* the counter-address on downconvert was... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add wishbone downconvert "skip" of slave sel so that... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add SysCon reg_info, has uart and has large SYSCON tree | commitdiff
2022-02-15 Luke Kenneth Casso... sigh, stall was not working but actually turns out... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add option to specify UART16550 width (32/8) tree | commitdiff
2022-02-15 Luke Kenneth Casso... add beginnings of syscon bus peripheral tree | commitdiff
2022-02-15 Luke Kenneth Casso... update comments tree | commitdiff
2022-02-15 Luke Kenneth Casso... resolve WBDownConvert ack issues when stall is active tree | commitdiff
2022-02-14 Luke Kenneth Casso... strip first 3 bits of WB address from microwatt d/i... tree | commitdiff
2022-02-14 Luke Kenneth Casso... slave sends stall signal, master receives, in tree | commitdiff
2022-02-14 Luke Kenneth Casso... sort out ExternalCore signal names tree | commitdiff
2022-02-14 Luke Kenneth Casso... add wishbone slave signal to downconvert if present tree | commitdiff
2022-02-14 Luke Kenneth Casso... add external core verilog wrapper, ironically around... tree | commitdiff
2022-02-13 Luke Kenneth Casso... bugfixing for ls2 imports of uart16550 tree | commitdiff
2022-02-13 Luke Kenneth Casso... Revert "remove dummy trap pipeline" tree | commitdiff
2022-02-13 Luke Kenneth Casso... Revert "doh" tree | commitdiff
2022-02-10 Andrey MiroshnikovAdded optional reverse arg to send TDI data MSB-first tree | commitdiff
2022-02-09 Luke Kenneth Casso... add opencores uart16550 instance wrapper tree | commitdiff
2022-01-31 Luke Kenneth Casso... fix bug in itlb_valid SRLatch set/reset, a bit weird... tree | commitdiff
2022-01-31 Luke Kenneth Casso... whoops tlb_valids in ICache is a combinatorial-get/set tree | commitdiff
2022-01-31 Luke Kenneth Casso... convert TLBValidArray in ICache to SRLatch tree | commitdiff
2022-01-31 Luke Kenneth Casso... use an SRLatch for cache_valids, at least it reduces... tree | commitdiff
2022-01-31 Luke Kenneth Casso... use Memory for cache tags in dcache tree | commitdiff
2022-01-31 Luke Kenneth Casso... use Memory for cache_tags in icache tree | commitdiff
2022-01-31 Luke Kenneth Casso... doh tree | commitdiff
2022-01-31 Luke Kenneth Casso... remove dummy trap pipeline tree | commitdiff
2022-01-31 Luke Kenneth Casso... remove combinatorial loop from MultiCompUnit tree | commitdiff
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