soc.git
2022-04-03 Luke Kenneth... add alternative pc_reset argument to issuer_verilog.py
2022-04-03 Luke Kenneth... fix some of instantiation errors in opencores_ethmac.py
2022-04-02 Raptor Engineering... Fix opencores EthMAC module wiring
2022-04-02 Cesar StraussImplement transparent read ports on the phased write...
2022-04-02 Cesar StraussImplement and test a "phased write port" memory
2022-03-31 Luke Kenneth... invert cs_n pin in Tercel
2022-03-30 Luke Kenneth... nope, default features in Tercel WB Buses need to not...
2022-03-29 Luke Kenneth... add bus.err to list of default Wishbone signals in...
2022-03-29 Luke Kenneth... byte-reverse Tercel read/write data and config bus...
2022-03-29 Luke Kenneth... set clock freq Constant length to 32-bit in Tercel.
2022-03-29 Luke Kenneth... self.specials does not exist, Instances must be added...
2022-03-29 Luke Kenneth... more sorting out wishbone names in Tercel
2022-03-29 Luke Kenneth... fix names of Instance signals in Tercel
2022-03-29 Luke Kenneth... sort out variable names in Tercel
2022-03-29 Luke Kenneth... self.comb does not exist, comb is a local temp-var...
2022-03-29 Luke Kenneth... whitespace cleanup (80 char limit)
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC
2022-03-27 Cesar StraussFinish the SRAM formal proof by implementing induction
2022-03-26 Cesar StraussAdd formal verification of the single port memory block
2022-03-26 Luke Kenneth... rename PLRU modules to avoid conflict in microwatt
2022-03-18 Luke Kenneth... whitespace cleanup (80 char limit, pep8)
2022-03-18 Luke Kenneth... turn CompALU/CompLDST latches synchronous
2022-03-16 Raptor Engineering... Add initial Tercel integration
2022-03-13 Cesar StraussSimulate some read/write/modify operations on the SRAM...
2022-03-13 Cesar StraussAdd a Single R/W Port SRAM model
2022-03-12 Luke Kenneth... add extra pipeline stages to ALU FU to make timing
2022-03-12 Luke Kenneth... introduce extra register of delay to split combinatoria...
2022-03-12 Luke Kenneth... Revert "read last row from r.wb.adr not r.req_adr in...
2022-03-12 Luke Kenneth... Revert "store cur_state.pc+4 in separate register to...
2022-03-12 Luke Kenneth... store cur_state.pc+4 in separate register to help reduce
2022-03-12 Luke Kenneth... read last row from r.wb.adr not r.req_adr in icache
2022-03-08 Luke Kenneth... remove stbs_done in icache.py
2022-03-08 Luke Kenneth... remove ld_stbs_done from dcache: not needed
2022-03-08 Luke Kenneth... work-in-progress on sdram opencores wrapper
2022-03-06 Cesar StraussCopy the startup delay from issuer.py to inorder.py
2022-02-28 Luke Kenneth... attempting to introduce an extra few clock cycles delay...
2022-02-27 Luke Kenneth... for lulz make I-Cache possible to set to 32-bit (XLEN=32)
2022-02-27 Luke Kenneth... bit_length is 1 more than needed: subtract 1 from XLEN...
2022-02-27 Luke Kenneth... fix up shift_rot test_pipe_caller to new regspeckls...
2022-02-27 Luke Kenneth... convert shift_rot pipeline to XLEN=32/64
2022-02-27 Luke Kenneth... fix up Logical pipeline to produce HDL with XLEN=32
2022-02-27 Luke Kenneth... whoops ALU common output target must be XLEN-bit,
2022-02-27 Luke Kenneth... set up dummy parent_pspec to pass XLEN=64 in
2022-02-27 Luke Kenneth... start on converting MUL and DIV pipelines to XLEN
2022-02-27 Luke Kenneth... convert from public static functions/properties for...
2022-02-27 Luke Kenneth... fix ALU with XLEN=32, carry and overflow
2022-02-27 Luke Kenneth... use XLEN in Function Units (starting with ALU)
2022-02-27 Luke Kenneth... add XLEN to issuer_verilog.py defaults to 64
2022-02-27 Luke Kenneth... add XLEN option to regfiles via pspec
2022-02-24 Jacob Lifshayadd running instructions
2022-02-24 Jacob Lifshayadd formal proof for shift/rot o.ok
2022-02-24 Jacob Lifshayclean up code
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCR
2022-02-24 Jacob Lifshayadd formal proof for OP_RLCL
2022-02-24 Jacob Lifshayadd formal proof for OP_RLC
2022-02-23 Luke Kenneth... forgot to pass cix (cache-inhibited) through to LD...
2022-02-22 Jacob Lifshayspeed up shift/rot formal proof by running stuff in...
2022-02-21 Luke Kenneth... again reduce combinatorial chains, similar to Trap...
2022-02-20 Luke Kenneth... add syn_ramstyle "block_ram" attributes and reduce...
2022-02-20 Luke Kenneth... same as shiftrot, split out separate pipelines for...
2022-02-20 Luke Kenneth... put LDST go-store on a 1-clock delay to help with combi...
2022-02-20 Luke Kenneth... name core_stop and terminated_o synchronous to potentia...
2022-02-20 Luke Kenneth... nope, it's perfectly fine
2022-02-20 Luke Kenneth... weird exception, oe not found in the shiftrot input...
2022-02-20 Luke Kenneth... separate out shiftrot stages due to size of main stage...
2022-02-18 Luke Kenneth... add blockram style to regfile Memory
2022-02-18 Luke Kenneth... use block_ram attribute for FPGA synthesis
2022-02-18 Luke Kenneth... reduce number of d-cache lines in microwatt fpga mode
2022-02-18 Luke Kenneth... couple of adjustments to reduce gate count in i/d-cache
2022-02-18 Luke Kenneth... add SDRAM Configuration Record
2022-02-18 Luke Kenneth... reduce TLB set size from 64 to 16 to get FPGA resource...
2022-02-18 Luke Kenneth... drastically reduce I-Cache size in microwatt-compat...
2022-02-18 Luke Kenneth... parameterise I-Cache similar to D-Cache. lots of "self."
2022-02-18 Jacob Lifshayadd grev
2022-02-17 Luke Kenneth... add opencores SDRAM verilog wrapper
2022-02-16 Luke Kenneth... oof. big update to DCache to accept config parameters
2022-02-16 Luke Kenneth... connect UART16550 pins if given
2022-02-15 Luke Kenneth... for *write* the counter-address on downconvert was...
2022-02-15 Luke Kenneth... add wishbone downconvert "skip" of slave sel so that...
2022-02-15 Luke Kenneth... add SysCon reg_info, has uart and has large SYSCON
2022-02-15 Luke Kenneth... sigh, stall was not working but actually turns out...
2022-02-15 Luke Kenneth... add option to specify UART16550 width (32/8)
2022-02-15 Luke Kenneth... add beginnings of syscon bus peripheral
2022-02-15 Luke Kenneth... update comments
2022-02-15 Luke Kenneth... resolve WBDownConvert ack issues when stall is active
2022-02-14 Luke Kenneth... strip first 3 bits of WB address from microwatt d/i...
2022-02-14 Luke Kenneth... slave sends stall signal, master receives, in
2022-02-14 Luke Kenneth... sort out ExternalCore signal names
2022-02-14 Luke Kenneth... add wishbone slave signal to downconvert if present
2022-02-14 Luke Kenneth... add external core verilog wrapper, ironically around...
2022-02-13 Luke Kenneth... bugfixing for ls2 imports of uart16550
2022-02-13 Luke Kenneth... Revert "remove dummy trap pipeline"
2022-02-13 Luke Kenneth... Revert "doh"
2022-02-10 Andrey MiroshnikovAdded optional reverse arg to send TDI data MSB-first
2022-02-09 Luke Kenneth... add opencores uart16550 instance wrapper
2022-02-01 Tobias Platencorrect path for make target microwatt_external_core
2022-01-31 Luke Kenneth... fix bug in itlb_valid SRLatch set/reset, a bit weird...
2022-01-31 Luke Kenneth... whoops tlb_valids in ICache is a combinatorial-get/set
2022-01-31 Luke Kenneth... convert TLBValidArray in ICache to SRLatch
2022-01-31 Luke Kenneth... add microwatt external core build target to Makefile
next