Remove redundant U/S mode advertisement
[riscv-isa-sim.git] / riscv / processor.cc
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-04-06 Andrew WatermanRemove non-standard uarch CSRs
2016-03-17 Andrew WatermanUpdate definition of base field in misa register
2016-03-04 Andrew WatermanFix up interrupt delegation
2016-03-02 Andrew WatermanAdd counter-enable registers
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanNew definitions of misa/marchid/mvendorid
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew Watermansptbr now a holds a PPN, not an address
2016-03-02 Andrew WatermanUse simpler MTVEC scheme
2016-03-02 Andrew WatermanZero-extend all CSR writes
2016-03-02 Andrew WatermanFix ERET serialization strategy
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-01-13 Andrew Watermandon't ignore data value when writing MIPI
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-26 Andrew WatermanFix histogram for RVC
2015-09-11 Andrew WatermanSimplify register_base_instructions
2015-09-11 Andrew WatermanInitialize mstatus.prv1/prv2 to U, not S
2015-09-11 Andrew WatermanSupport 'G' in ISA strings
2015-09-09 Andrew WatermanImprove instruction fetch
2015-07-30 Christopher CelioAdded error message when trying to use histogram
2015-07-05 Andrew WatermanNew machine-mode timer facility
2015-06-01 Andrew WatermanUse single, shared real-time counter
2015-06-01 Andrew WatermanExecute exactly the # of insns passed to step()
2015-06-01 Andrew WatermanFix performance bug when CSR accesses are common
2015-06-01 Andrew WatermanTake interrupts as soon as interrupts are enabled
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-30 Andrew WatermanFix commit log for CSR instructions
2015-04-04 Andrew WatermanCheck for F extension when accessing FCSR
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-31 Andrew WatermanAllow writing mstatus.fs even if FPU isn't present
2015-03-27 Andrew WatermanSerialize counters without throwing C++ exceptions
2015-03-26 Andrew WatermanUpdate state.pc on every instruction
2015-03-17 Yunsup Leebugfix, mbadaddr should be writable
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-27 Christopher CelioFixed masking/casting logic in commit log printf.
2015-01-26 Andrew WatermanFix commit log
2015-01-02 Andrew WatermanReduce dependences on auto-generated code
2014-12-05 Andrew WatermanSupport 2/4/6/8-byte instructions
2014-12-01 Andrew WatermanImplement timer faithfully
2014-08-15 Christopher CelioAdded PC histogram option.
2014-08-08 Andrew WatermanSupport uarch counters (degenerately)
2014-07-08 Andrew WatermanDisallow access to FCSR when FP is disabled
2014-07-07 Andrew WatermanMinor refactoring
2014-06-13 Christopher CelioCommit log now prints while interrupts are enabled.
2014-06-13 Andrew WatermanOnly print commit log if instruction commits
2014-06-12 Andrew WatermanSet status.u64 to true on boot
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-15 Andrew Watermanspeed up compilation a bit
2014-02-14 Andrew WatermanFix I$ simulator not making forward progress
2014-02-12 Andrew WatermanFix commit log when !debug
2014-02-07 Andrew WatermanClear EVEC LSBs, which kindly prevents a segfault
2014-01-24 Andrew WatermanHandle CSR permissions correctly
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-16 Andrew WatermanInitialize tohost and fromhost to zero
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-19 Yunsup Leeclean up SR_EA, the enable accelerator bit in status reg
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-10-16 Yunsup Leefix missing null check when there's no extension
2013-10-15 Stephen TwiggPropogate the reset call to the extensions as well...
2013-09-27 Christopher CelioAdded commit logging (--enable-commitlog). Also fixed...
2013-09-23 Scott Beamerfixes compile bug for not being able to find std::logic...
2013-09-11 Andrew WatermanImplement zany immediates
2013-08-18 Andrew WatermanRenumber PCRs
2013-08-13 Andrew WatermanImplement RoCC and add a dummy RoCC
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-26 Andrew WatermanRip out Hwacha for now
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-07-22 Andrew WatermanAdd xspike program
2013-04-25 Andrew Watermanuse inttypes macros to print uint64_t
2013-04-24 Yunsup Leefixes to correctly simulate the vector unit
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-30 Andrew Watermanignore writes to SR IP field
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-03-26 Andrew Watermanexpose pending interrupts in status register
2013-02-13 Andrew Watermanclean up fetch-execute loop a bit
2012-11-13 Yunsup Leefix vector code simulation problem, turn on SR_U64
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-08-02 Andrew Watermannew tohost/fromhost semantics
2012-07-23 Andrew Watermancorrect HTIF reset behavior
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-03-20 Andrew Watermanabstract regfile behind object
2011-12-11 Yunsup Leefix utidx assign bug, make ut code execute faster
2011-11-12 Your NameRemove dependence on binutils
2011-11-11 Andrew WatermanUse new compiler toolchain's disassembler
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
next