| 2019-06-28 |
Luke Kenneth Casso... | remove ssvoffs from SVSTATE |
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| 2019-06-27 |
Luke Kenneth Casso... | add sesvstate / mesvstate, set on entry to trap |
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| 2019-06-27 |
Luke Kenneth Casso... | add subvl to headers, comment out state-cfg |
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| 2018-11-15 |
Luke Kenneth Casso... | add predication remap option |
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| 2018-11-13 |
Luke Kenneth Casso... | alter set_csr to call get_csr, will make csrrw* easier |
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| 2018-11-13 |
Luke Kenneth Casso... | redo SV CSRs to use a stack-based mechanism |
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| 2018-11-05 |
Luke Kenneth Casso... | correct bank and size, use in setting up CSR tables |
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| 2018-11-05 |
Luke Kenneth Casso... | move csr reg and predicate table unpack to separate... |
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| 2018-11-05 |
Luke Kenneth Casso... | add state and bank sv csr bitfields |
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| 2018-11-03 |
Luke Kenneth Casso... | add reshape data structures and get_shape function |
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| 2018-11-03 |
Luke Kenneth Casso... | add state redirection for CSR get/set depending on... |
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| 2018-11-02 |
Luke Kenneth Casso... | expand register size to 128 long, add exceptions if... |
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| 2018-11-02 |
Luke Kenneth Casso... | increase regfile sizes to 128 entries |
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| 2018-10-18 |
Luke Kenneth Casso... | put sv_mmu override class in place |
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| 2018-10-14 |
Luke Kenneth Casso... | bit of a mess: attempted to create a complete arithmeti... |
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| 2018-10-11 |
Luke Kenneth Casso... | redirect instructions through a class called sv_proc_t |
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| 2018-10-05 |
Luke Kenneth Casso... | reorganise src and dest vector-element offsets |
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| 2018-10-05 |
Luke Kenneth Casso... | add srcoffs and destoffs sv state, alter CSRs |
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| 2018-09-29 |
Luke Kenneth Casso... | have to move SV CSRs into processor_t |
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| 2018-09-29 |
Luke Kenneth Casso... | revert addition of svsetvl as an actual opcode, add... |
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| 2018-09-27 |
Luke Kenneth Casso... | adding sv vector length CSR to processor state, and... |
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| 2018-07-10 |
Andrew Waterman | Refactor and fix LR/SC implementation (#217) |
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| 2018-03-22 |
Andrew Waterman | Implement Hauser misa.C misalignment proposal (#187) |
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| 2018-03-16 |
Andrew Waterman | Merge branch 'deepsrc-b_fix_issue183' |
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| 2018-03-14 |
Prashanth Mundkur | Fix a bug caused by moving misa into state_t. (#180) |
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| 2018-03-13 |
Prashanth Mundkur | Move processor.isa to state.misa, since it really belon... |
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| 2018-03-08 |
Tim Newsome | Merge pull request #177 from riscv/debug_auth |
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| 2018-03-06 |
Prashanth Mundkur | Narrow the interface used by the processors and memory... |
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| 2018-03-06 |
Prashanth Mundkur | Fix install of a missed header from debug_rom. |
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| 2018-03-03 |
Andrew Waterman | Implement clearing-misa.C-while-PC-is-misaligned proposal |
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| 2017-11-27 |
Andrew Waterman | Rename badaddr to tval |
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| 2017-11-27 |
Andrew Waterman | Rename sptbr to satp |
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| 2017-11-16 |
Andrew Waterman | Merge pull request #156 from p12nGH/noncontiguous_harts |
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| 2017-11-10 |
Andrew Waterman | H-mode no longer exists |
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| 2017-11-10 |
Andrew Waterman | MPP is now WARL |
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| 2017-10-20 |
Andrew Waterman | Fix commit-log for Q extension, and for RV32 (#143) |
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| 2017-09-21 |
Tim Newsome | Fix corner case in repeated execution (#127) |
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| 2017-08-10 |
Tim Newsome | Merge pull request #117 from riscv/multicore_debug |
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| 2017-08-07 |
Tim Newsome | Fix multicore debug. |
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| 2017-05-17 |
Palmer Dabbelt | Merge remote-tracking branch 'origin/priv-1.10' |
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| 2017-05-16 |
Palmer Dabbelt | Merge remote-tracking branch 'origin/debug-0.13' into... |
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| 2017-04-18 |
Megan Wachs | debug: Checkpoint which somewhat works with OpenOCD... |
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| 2017-04-18 |
Megan Wachs | debug: Move things around, but addresses now conflict... |
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| 2017-04-17 |
Megan Wachs | Merge remote-tracking branch 'origin/priv-1.10' into... |
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| 2017-03-22 |
Wesley W. Terpstra | riscv: replace rtc device with a real clint implementation |
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| 2017-02-25 |
Andrew Waterman | New counter enable scheme |
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| 2017-02-11 |
Tim Newsome | Entering debug mode now jumps to "dynamic rom" |
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| 2017-02-10 |
Tim Newsome | Implement hartstatus field. |
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| 2017-02-07 |
Tim Newsome | Merge pull request #83 from bacam/gdb-protocol-fixes |
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| 2017-02-03 |
Andrew Waterman | Fix interrupt delegation for coprocessors |
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| 2016-09-10 |
Andrew Waterman | allow MAFDC bits in MISA to be modified |
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| 2016-09-02 |
Andrew Waterman | Merge pull request #62 from riscv/trigger |
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| 2016-09-02 |
Tim Newsome | Merge branch 'master' into trigger |
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| 2016-08-31 |
Tim Newsome | Rename tdata[0-2] to tdata[1-3]. |
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| 2016-08-29 |
Tim Newsome | Rename tdata0--tdata2 to tdata1--tdata3. |
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| 2016-08-27 |
Andrew Waterman | Add (degenerate) performance counter facility |
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| 2016-08-26 |
Andrew Waterman | partially update spike to newer debug spec |
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| 2016-08-26 |
Andrew Waterman | Fix spike interactive (-d) mode |
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| 2016-08-22 |
Tim Newsome | Implement address and data triggers. |
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| 2016-08-17 |
Andrew Waterman | Allow mstatus.MPP to store bad values; instead, validat... |
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| 2016-07-28 |
Tim Newsome | Add support for virtual priv register. (#59) |
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| 2016-06-29 |
Andrew Waterman | Disassemble RVC instructions based on XLEN |
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| 2016-06-23 |
Andrew Waterman | Remove legacy HTIF; implement HTIF directly |
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| 2016-06-23 |
Andrew Waterman | Fix paddr_bits computation prior to VM setup |
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| 2016-05-23 |
Tim Newsome | Make -H halt the core right out of reset. |
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| 2016-05-23 |
Tim Newsome | Single step appears to work. |
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| 2016-05-23 |
Tim Newsome | processor_t unfriends gdbserver_t. |
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| 2016-05-23 |
Tim Newsome | Add debug_module bus device. |
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| 2016-05-23 |
Tim Newsome | When gdb connects, jump to Debug ROM and segfault. |
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| 2016-05-23 |
Tim Newsome | Gutting direct-access gdb. |
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| 2016-05-23 |
Tim Newsome | Add writing to DCSR, DPC, DSCRATCH. |
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| 2016-05-23 |
Tim Newsome | Flush icache when using swbps and report to gdb. |
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| 2016-05-23 |
Tim Newsome | Looks like single step works. |
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| 2016-05-23 |
Tim Newsome | Now you can halt/continue from gdb. |
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| 2016-05-23 |
Tim Newsome | gdb can now read spike memory. |
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| 2016-05-02 |
Andrew Waterman | Remove tohost/fromhost registers |
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| 2016-04-29 |
Andrew Waterman | Move much closer to new platform-M memory map |
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| 2016-04-28 |
Andrew Waterman | Remove MTIME[CMP]; add RTC device |
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| 2016-03-02 |
Andrew Waterman | Add counter-enable registers |
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| 2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
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| 2016-03-02 |
Andrew Waterman | New definitions of misa/marchid/mvendorid |
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| 2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
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| 2015-12-17 |
Scott Beamer | another osx clang compatability fix |
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| 2015-11-13 |
Andrew Waterman | Generate device tree for target machine |
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| 2015-10-26 |
Andrew Waterman | Fix histogram for RVC |
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| 2015-09-16 |
Scott Beamer | commit log now correctly prints privilege |
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| 2015-09-09 |
Andrew Waterman | Improve instruction fetch |
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| 2015-07-05 |
Andrew Waterman | New machine-mode timer facility |
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| 2015-06-01 |
Andrew Waterman | Use single, shared real-time counter |
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| 2015-06-01 |
Andrew Waterman | Take interrupts as soon as interrupts are enabled |
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| 2015-05-09 |
Andrew Waterman | Upgrade to privileged architecture 1.7 |
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| 2015-04-04 |
Andrew Waterman | Support setting ISA/subsets with --isa flag |
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| 2015-03-27 |
Andrew Waterman | Serialize counters without throwing C++ exceptions |
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| 2015-03-13 |
Andrew Waterman | Update to new privileged spec |
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| 2015-01-26 |
Andrew Waterman | Fix commit log |
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| 2014-12-01 |
Andrew Waterman | Implement timer faithfully |
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| 2014-08-15 |
Christopher Celio | Added PC histogram option. |
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| 2014-06-13 |
Andrew Waterman | Only print commit log if instruction commits |
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| 2014-04-03 |
Stephen Twigg | Merge branch 'tm' |
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| 2014-03-15 |
Andrew Waterman | speed up compilation a bit |
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