git.libre-soc.org Git - riscv-isa-sim.git/shortlog

2017-03-22	Wesley W. Terpstra	sim: declare cores as interrupt-controllers for clint	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	bootrom: set a0 to hartid and a1 to dtb before boot	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	configstring: rename variables to dts	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	riscv: remove dependency on num_cores	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	bootrom: include compiled dtb	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	sim: create DTS instead of config string	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	sim: define emulated CPU clock rate to be 1GHz	commit \| commitdiff \| tree
2017-03-21	Wesley W. Terpstra	autoconf: put location of 'dtc' into config.h	commit \| commitdiff \| tree
2017-03-21	Palmer Dabbelt	spec bump	commit \| commitdiff \| tree
2017-03-20	Andrew Waterman	PUM -> SUM; expose MXR to S-mode	commit \| commitdiff \| tree
2017-03-16	Andrew Waterman	Simplify interrupt-stack discipline	commit \| commitdiff \| tree
2017-03-13	Andrew Waterman	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	commit \| commitdiff \| tree
2017-03-07	Andrew Waterman	Don't overload illegal instruction trap in interactive...	commit \| commitdiff \| tree
2017-02-27	Andrew Waterman	Sv57 and Sv64 are not spec'd yet	commit \| commitdiff \| tree
2017-02-25	Andrew Waterman	New counter enable scheme	commit \| commitdiff \| tree
2017-02-25	Tim Newsome	Update bits to latest spec.	commit \| commitdiff \| tree
2017-02-23	Tim Newsome	Implement halt request.	commit \| commitdiff \| tree
2017-02-22	Tim Newsome	Improve debug performance.	commit \| commitdiff \| tree
2017-02-22	Tim Newsome	Don't waste time spinning in place in debug mode	commit \| commitdiff \| tree
2017-02-21	Andrew Waterman	serialize simulator on wfi	commit \| commitdiff \| tree
2017-02-21	Andrew Waterman	Take M-mode interrupts over S-mode interrupts	commit \| commitdiff \| tree
2017-02-21	Andrew Waterman	permit MMIO loads to MSIP bit	commit \| commitdiff \| tree
2017-02-19	Andrew Waterman	Make HW setting of PTE A/D bits optional (by configure...	commit \| commitdiff \| tree
2017-02-18	Andrew Waterman	Spike uarch needs TLB flush after SPTBR write	commit \| commitdiff \| tree
2017-02-18	Tim Newsome	Compress log output of jump-to-self loops.	commit \| commitdiff \| tree
2017-02-16	Tim Newsome	Remove noisy debugs.	commit \| commitdiff \| tree
2017-02-16	Tim Newsome	Set cmderr when data is accessed while busy.	commit \| commitdiff \| tree
2017-02-16	Tim Newsome	Implement autoexec. DMI op 2 is just write now.	commit \| commitdiff \| tree
2017-02-15	Tim Newsome	Implement resume (untested).	commit \| commitdiff \| tree
2017-02-15	Andrew Waterman	sfence.vm -> sfence.vma	commit \| commitdiff \| tree
2017-02-14	Tim Newsome	Implement program buffer preexec/postexec.	commit \| commitdiff \| tree
2017-02-13	Tim Newsome	dbus -> dmi	commit \| commitdiff \| tree
2017-02-13	Tim Newsome	Abstract register read mostly working.	commit \| commitdiff \| tree
2017-02-12	Tim Newsome	Fix stack overflow and support --rbb-port=0	commit \| commitdiff \| tree
2017-02-11	Tim Newsome	Entering debug mode now jumps to "dynamic rom"	commit \| commitdiff \| tree
2017-02-10	Tim Newsome	Implement hartstatus field.	commit \| commitdiff \| tree
2017-02-10	Tim Newsome	Remove gdbserver support.	commit \| commitdiff \| tree
2017-02-09	Tim Newsome	Add writable ibuf and data registers.	commit \| commitdiff \| tree
2017-02-09	Tim Newsome	Serve up a correct dmcontrol register.	commit \| commitdiff \| tree
2017-02-08	Andrew Waterman	Encode VM type in sptbr, not mstatus	commit \| commitdiff \| tree
2017-02-07	Tim Newsome	OpenOCD does a dmi read and gets dummy value back.	commit \| commitdiff \| tree
2017-02-07	Tim Newsome	Merge pull request #83 from bacam/gdb-protocol-fixes	commit \| commitdiff \| tree
2017-02-07	Tim Newsome	Remove unnecessary circular buffer code.	commit \| commitdiff \| tree
2017-02-07	Tim Newsome	Refactor remote bitbang code.	commit \| commitdiff \| tree
2017-02-03	Tim Newsome	OpenOCD RISC-V code now gets to scan out dtmcontrol.	commit \| commitdiff \| tree
2017-02-03	Tim Newsome	OpenOCD can now scan out the hacked IDCODE.	commit \| commitdiff \| tree
2017-02-03	Tim Newsome	OpenOCD connects, and sends some data that we receive.	commit \| commitdiff \| tree
2017-02-03	Andrew Waterman	Fix interrupt delegation for coprocessors	commit \| commitdiff \| tree
2017-02-02	Andrew Waterman	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonica...	commit \| commitdiff \| tree
2017-02-02	Andrew Waterman	Set xPIE=1 on xRET	commit \| commitdiff \| tree
2017-01-08	Andrew Waterman	Only allow SIP.SSIP to be toggled if the interrupt...	commit \| commitdiff \| tree
2017-01-08	Andrew Waterman	Make SIP.STIP read-only	commit \| commitdiff \| tree
2017-01-06	David Craven	Comply with GNU coding standards.	commit \| commitdiff \| tree
2016-12-30	Brian Campbell	Only read exception flag in gdb register read/write...	commit \| commitdiff \| tree
2016-12-21	Brian Campbell	Fix gdb communication error (#82)	commit \| commitdiff \| tree
2016-12-21	Brian Campbell	Remove extra gdb protocol responses on register writes	commit \| commitdiff \| tree
2016-12-21	Brian Campbell	Fix gdb protocol register read of S0	commit \| commitdiff \| tree
2016-12-17	Stefan O'Rear	Use correct format codes for reg_t and size_t	commit \| commitdiff \| tree
2016-12-16	Tim Newsome	Fix single stepping over faulting instructions. (#80)	commit \| commitdiff \| tree
2016-12-12	Tim Newsome	Reuse the ebreak constants in encoding.h.	commit \| commitdiff \| tree
2016-12-01	Andy Wright	Added comments about the modified Duff's Device in...	commit \| commitdiff \| tree
2016-11-14	Andrew Waterman	Fix 32-bit host portability bug	commit \| commitdiff \| tree
2016-11-12	Ben Gamari	Ensure that g++ knows it is building a PCH (#75)	commit \| commitdiff \| tree
2016-11-10	Andrew Waterman	AMOs should always return store faults, not load faults	commit \| commitdiff \| tree
2016-10-31	Tim Newsome	Make reading/writing fpu regs work.	commit \| commitdiff \| tree
2016-10-31	Tim Newsome	Minor code cleanup.	commit \| commitdiff \| tree
2016-10-31	Tim Newsome	Check for exception after register write.	commit \| commitdiff \| tree
2016-10-28	Tim Newsome	Check for exception after reading a register.	commit \| commitdiff \| tree
2016-10-28	Tim Newsome	Fix error message.	commit \| commitdiff \| tree
2016-10-25	Tim Newsome	Increase gdb receive buffer.	commit \| commitdiff \| tree
2016-10-10	Andrew Waterman	Don't force load trigger timing to After	commit \| commitdiff \| tree
2016-10-07	Tim Newsome	Don't die when gdb thinks XLEN is 64 but it's 32.	commit \| commitdiff \| tree
2016-09-30	Tim Newsome	Return an error to gdb when memory reads fail. (#71)	commit \| commitdiff \| tree
2016-09-29	Tim Newsome	Update trigger behavior. (#70)	commit \| commitdiff \| tree
2016-09-13	Scott Beamer	restore clang support by fixing printf identifiers	commit \| commitdiff \| tree
2016-09-10	Andrew Waterman	allow MAFDC bits in MISA to be modified	commit \| commitdiff \| tree
2016-09-06	Tim Newsome	Remove generic debug tests. (#65)	commit \| commitdiff \| tree
2016-09-02	Andrew Waterman	Merge pull request #62 from riscv/trigger	commit \| commitdiff \| tree
2016-09-02	Tim Newsome	Merge branch 'master' into trigger	commit \| commitdiff \| tree
2016-09-02	Tim Newsome	Rebuild debug ROM because CSR encoding changed.	commit \| commitdiff \| tree
2016-09-02	Tim Newsome	Support triggers on TLB misses.	commit \| commitdiff \| tree
2016-09-01	Tim Newsome	Theoretically support trigger timing.	commit \| commitdiff \| tree
2016-08-31	Tim Newsome	Rename tdata[0-2] to tdata[1-3].	commit \| commitdiff \| tree
2016-08-31	Tim Newsome	Save/restore tselect. Set dmode.	commit \| commitdiff \| tree
2016-08-29	Tim Newsome	Fix indent.	commit \| commitdiff \| tree
2016-08-29	Tim Newsome	Rename tdata0--tdata2 to tdata1--tdata3.	commit \| commitdiff \| tree
2016-08-27	Andrew Waterman	Add (degenerate) performance counter facility	commit \| commitdiff \| tree
2016-08-26	Andrew Waterman	Allow reads from tdrdata registers	commit \| commitdiff \| tree
2016-08-26	Andrew Waterman	partially update spike to newer debug spec	commit \| commitdiff \| tree
2016-08-26	Andrew Waterman	Fix spike interactive (-d) mode	commit \| commitdiff \| tree
2016-08-23	Andrew Waterman	remove HWBPCOUNT field of DCSR	commit \| commitdiff \| tree
2016-08-22	Tim Newsome	Implement address and data triggers.	commit \| commitdiff \| tree
2016-08-17	Andrew Waterman	Allow mstatus.MPP to store bad values; instead, validat...	commit \| commitdiff \| tree
2016-08-16	Colin Schmidt	remove old rvc directory (#61)	commit \| commitdiff \| tree
2016-07-28	Tim Newsome	Add support for virtual priv register. (#59)	commit \| commitdiff \| tree
2016-07-22	Andrew Waterman	Set U bit in misa register	commit \| commitdiff \| tree
2016-07-19	Tim Newsome	Make address translation work in 32-bit. (#58)	commit \| commitdiff \| tree
2016-07-13	Tim Newsome	Fix single step over csrw instructions. (#57)	commit \| commitdiff \| tree
2016-07-12	Andrew Waterman	Don't treat RVC NOP as illegal instruction	commit \| commitdiff \| tree
2016-07-12	Andrew Waterman	Fix page table walker not respecting valid bit	commit \| commitdiff \| tree
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