| 2022-03-12 |
Luke Kenneth Casson... | add extra pipeline stages to ALU FU to make timing
|
commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | introduce extra register of delay to split combinatorial...
|
commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | Revert "read last row from r.wb.adr not r.req_adr in...
|
commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | Revert "store cur_state.pc+4 in separate register to...
|
commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | store cur_state.pc+4 in separate register to help reduce
|
commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | read last row from r.wb.adr not r.req_adr in icache
|
commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | remove stbs_done in icache.py
|
commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | remove ld_stbs_done from dcache: not needed
|
commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | work-in-progress on sdram opencores wrapper
|
commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | attempting to introduce an extra few clock cycles delay...
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | for lulz make I-Cache possible to set to 32-bit (XLEN=32)
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | bit_length is 1 more than needed: subtract 1 from XLEN...
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix up shift_rot test_pipe_caller to new regspeckls...
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | convert shift_rot pipeline to XLEN=32/64
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix up Logical pipeline to produce HDL with XLEN=32
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | whoops ALU common output target must be XLEN-bit,
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | set up dummy parent_pspec to pass XLEN=64 in
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | start on converting MUL and DIV pipelines to XLEN
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | convert from public static functions/properties for...
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix ALU with XLEN=32, carry and overflow
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | use XLEN in Function Units (starting with ALU)
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | add XLEN to issuer_verilog.py defaults to 64
|
commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | add XLEN option to regfiles via pspec
|
commit | commitdiff | tree |
| 2022-02-23 |
Luke Kenneth Casson... | forgot to pass cix (cache-inhibited) through to LD...
|
commit | commitdiff | tree |
| 2022-02-21 |
Luke Kenneth Casson... | again reduce combinatorial chains, similar to Trap...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | add syn_ramstyle "block_ram" attributes and reduce...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | same as shiftrot, split out separate pipelines for...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | put LDST go-store on a 1-clock delay to help with combinator...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | name core_stop and terminated_o synchronous to potentially...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | nope, it's perfectly fine
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | weird exception, oe not found in the shiftrot input...
|
commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | separate out shiftrot stages due to size of main stage...
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add blockram style to regfile Memory
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | use block_ram attribute for FPGA synthesis
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | reduce number of d-cache lines in microwatt fpga mode
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | couple of adjustments to reduce gate count in i/d-cache
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add SDRAM Configuration Record
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | reduce TLB set size from 64 to 16 to get FPGA resource...
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | drastically reduce I-Cache size in microwatt-compat...
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | parameterise I-Cache similar to D-Cache. lots of "self."
|
commit | commitdiff | tree |
| 2022-02-17 |
Luke Kenneth Casson... | add opencores SDRAM verilog wrapper
|
commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | oof. big update to DCache to accept config parameters
|
commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | connect UART16550 pins if given
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | for *write* the counter-address on downconvert was...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add wishbone downconvert "skip" of slave sel so that...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add SysCon reg_info, has uart and has large SYSCON
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | sigh, stall was not working but actually turns out...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add option to specify UART16550 width (32/8)
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add beginnings of syscon bus peripheral
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | update comments
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | resolve WBDownConvert ack issues when stall is active
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | strip first 3 bits of WB address from microwatt d/i...
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | slave sends stall signal, master receives, in
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | sort out ExternalCore signal names
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add wishbone slave signal to downconvert if present
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add external core verilog wrapper, ironically around...
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | bugfixing for ls2 imports of uart16550
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "remove dummy trap pipeline"
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "doh"
|
commit | commitdiff | tree |
| 2022-02-09 |
Luke Kenneth Casson... | add opencores uart16550 instance wrapper
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | fix bug in itlb_valid SRLatch set/reset, a bit weird...
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | whoops tlb_valids in ICache is a combinatorial-get/set
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | convert TLBValidArray in ICache to SRLatch
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | add microwatt external core build target to Makefile
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use an SRLatch for cache_valids, at least it reduces...
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache tags in dcache
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache_tags in icache
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | doh
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove dummy trap pipeline
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove combinatorial loop from MultiCompUnit
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | break out cache_tags and cache_valids (again) this...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove CacheTagArray in icache.py
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | create Memory for Cache Tags in I-Cache
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove unneeded parameter
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | add Array of CacheValids back in, so as to reduce LUT4...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | tagset is a local Signal in ICache
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | identify combinatorial loop signals in MultiCompUnit...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | use nmigen Memory in I-Cache for TLB Lookups
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | put itlb_valid back, ready for conversion to Memory...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | convert CacheRAM to Memory, acts much faster now
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | explanatory comment when page hit is the same for stores
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | use right offset in dcache wb address
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | re-examining dcache.vhdl, still did not get the store...
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | bug in dcache.py where when two stores occur in the...
|
commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | in LoadStore1 capture the address for misaligned dual...
|
commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | sort out misaligned store in LoadStore1
|
commit | commitdiff | tree |
| 2022-01-27 |
Luke Kenneth Casson... | for second aligned request truncate address to nearest...
|
commit | commitdiff | tree |
| 2022-01-25 |
Luke Kenneth Casson... | add license and copyright header to dcache.py,
|
commit | commitdiff | tree |
| 2022-01-25 |
Luke Kenneth Casson... | LDSTException now passing bits of SRR1 around to the...
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | hmm there seems to have been an error in DTLB Read,
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | bool test on traptype to
|
commit | commitdiff | tree |
| 2022-01-23 |
Luke Kenneth Casson... | looked in soc.vhdl in microwatt and the parameters...
|
commit | commitdiff | tree |
| 2022-01-23 |
Luke Kenneth Casson... | add debug output of whether stall occurs on dcache
|
commit | commitdiff | tree |
| 2022-01-22 |
Luke Kenneth Casson... | missed setting of r0_full to zero in dcache. not encountered as
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | skip ilang data in branch test_pipe_caller.py
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | attempting to get compunit and test_pipe_caller unit...
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | sigh, monitor DEC/TB StateRegs "properly" so that the...
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | whoops fix bug in setting of DEC/TB (State) in test_core.py
|
commit | commitdiff | tree |
| 2022-01-20 |
Luke Kenneth Casson... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
|
commit | commitdiff | tree |
| next |
projects / soc.git / search