Move much closer to new platform-M memory map
[riscv-isa-sim.git] / riscv / mmu.cc
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew Watermansptbr now a holds a PPN, not an address
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-02-04 Andrew WatermanActually refill ITLB on ITLB miss
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-13 Andrew WatermanFix --dc flag
2015-09-25 Andrew WatermanRefactor memory access code; add MMIO support
2015-09-25 Andrew WatermanUse enum instead of two bools to denote memory access...
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-26 Andrew WatermanFix I$ simulator hit count
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-14 Andrew WatermanDon't set dirty/referenced bits w/o permission
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-02 Andrew WatermanReduce dependences on auto-generated code
2014-12-05 Andrew WatermanSet badvaddr on instruction page faults
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-02-15 Andrew Watermandon't store host pointers in soft TLB
2013-02-13 Andrew Watermanclean up fetch-execute loop a bit
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2012-03-24 Andrew Watermannew supervisor mode
2012-01-31 Andrew Watermandon't set badvaddr for instruction access faults
2012-01-24 Andrew Watermancheck that virtual addresses are sign-extended
2011-11-01 Andrew WatermanFixed tight coupling of host and target page size
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] tlb now stores host addresses
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support