| 2022-02-18 |
Luke Kenneth Casso... | add SDRAM Configuration Record |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | reduce TLB set size from 64 to 16 to get FPGA resource... |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | drastically reduce I-Cache size in microwatt-compat... |
tree | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | parameterise I-Cache similar to D-Cache. lots of "self." |
tree | commitdiff |
| 2022-02-18 |
Jacob Lifshay | add grev |
tree | commitdiff |
| 2022-02-17 |
Luke Kenneth Casso... | add opencores SDRAM verilog wrapper |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | oof. big update to DCache to accept config parameters |
tree | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | connect UART16550 pins if given |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | for *write* the counter-address on downconvert was... |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add wishbone downconvert "skip" of slave sel so that... |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add SysCon reg_info, has uart and has large SYSCON |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | sigh, stall was not working but actually turns out... |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add option to specify UART16550 width (32/8) |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | add beginnings of syscon bus peripheral |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | update comments |
tree | commitdiff |
| 2022-02-15 |
Luke Kenneth Casso... | resolve WBDownConvert ack issues when stall is active |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | strip first 3 bits of WB address from microwatt d/i... |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | slave sends stall signal, master receives, in |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | sort out ExternalCore signal names |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | add wishbone slave signal to downconvert if present |
tree | commitdiff |
| 2022-02-14 |
Luke Kenneth Casso... | add external core verilog wrapper, ironically around... |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | bugfixing for ls2 imports of uart16550 |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "remove dummy trap pipeline" |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "doh" |
tree | commitdiff |
| 2022-02-10 |
Andrey Miroshnikov | Added optional reverse arg to send TDI data MSB-first |
tree | commitdiff |
| 2022-02-09 |
Luke Kenneth Casso... | add opencores uart16550 instance wrapper |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | fix bug in itlb_valid SRLatch set/reset, a bit weird... |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | whoops tlb_valids in ICache is a combinatorial-get/set |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | convert TLBValidArray in ICache to SRLatch |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | use an SRLatch for cache_valids, at least it reduces... |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | use Memory for cache tags in dcache |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | use Memory for cache_tags in icache |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | doh |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | remove dummy trap pipeline |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | remove combinatorial loop from MultiCompUnit |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | break out cache_tags and cache_valids (again) this... |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | remove CacheTagArray in icache.py |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | create Memory for Cache Tags in I-Cache |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | remove unneeded parameter |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | add Array of CacheValids back in, so as to reduce LUT4... |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | tagset is a local Signal in ICache |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | identify combinatorial loop signals in MultiCompUnit... |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | use nmigen Memory in I-Cache for TLB Lookups |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | put itlb_valid back, ready for conversion to Memory... |
tree | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | convert CacheRAM to Memory, acts much faster now |
tree | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | explanatory comment when page hit is the same for stores |
tree | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | use right offset in dcache wb address |
tree | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | re-examining dcache.vhdl, still did not get the store... |
tree | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | bug in dcache.py where when two stores occur in the... |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | in LoadStore1 capture the address for misaligned dual... |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | sort out misaligned store in LoadStore1 |
tree | commitdiff |
| 2022-01-27 |
Luke Kenneth Casso... | for second aligned request truncate address to nearest... |
tree | commitdiff |
| 2022-01-25 |
Luke Kenneth Casso... | add license and copyright header to dcache.py, |
tree | commitdiff |
| 2022-01-25 |
Luke Kenneth Casso... | LDSTException now passing bits of SRR1 around to the... |
tree | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | comments |
tree | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | hmm there seems to have been an error in DTLB Read, |
tree | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | bool test on traptype to |
tree | commitdiff |
| 2022-01-23 |
Luke Kenneth Casso... | looked in soc.vhdl in microwatt and the parameters... |
tree | commitdiff |
| 2022-01-23 |
Luke Kenneth Casso... | add debug output of whether stall occurs on dcache |
tree | commitdiff |
| 2022-01-22 |
Luke Kenneth Casso... | missed setting of r0_full to zero in dcache. not encoun... |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | skip ilang data in branch test_pipe_caller.py |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | attempting to get compunit and test_pipe_caller unit... |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | sigh, monitor DEC/TB StateRegs "properly" so that the... |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | whoops fix bug in setting of DEC/TB (State) in test_core.py |
tree | commitdiff |
| 2022-01-20 |
Luke Kenneth Casso... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | whoops forgot to enable fast-reg read in DMI |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | ISI (0x400) trap is the only one that puts memory-based... |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | comments |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | move DEC and TB into StateRegs, to make room in FastRegs |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | add support for DMI debug read of FAST Regfile SPRs |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | comments on SRR1 in trap |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | preserve bits of SRR1 on a TRAP (including all interrup... |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | fix hrfid and mtmsrd so that it is identical to microwatt |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | connect up DEC/TB FSM pauser from core to Issuer |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | comments |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | add pause_dec_tb signal (not very sophisticated) to... |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | add signal for pausing the DEC/TB FSM to IssuerBase |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | raise interrupt on misaligned atomic LDST |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | pass over store_done correctly from dcache over PortInt... |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | add CR0 to LDSTCompUnit, for reporting if LR/SC store... |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | remove PortInterface mmu_done signal, |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | forgot name on dcache Reservation |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass over atomic signals to dcache from loadstore. |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | try using req.op in RELOAD_WAIT_ACK to detect whether... |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass atomic reserve through from PortInterface to DCache |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | add atomic LR/SC signal to LDSTCompUnit |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | add reserve (atomic) signal to LDST data structures... |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | tidyup PortInterface |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | workaround for bug in dcache where the r1.req waiting... ldst_misalign |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | enable both linux-5.7 tests |
tree | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | split out CacheTag Record to separate structure |
tree | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | update how d_valid is handled |
tree | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | missed setting r1.store_way and r1.store_row in STORE_W... |
tree | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | Revert "dcache 2nd stage (r1) should only indicate... |
tree | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | second test for linux-5.7 |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | add allow-overlap option to issuer_verilog.py |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | dcache 2nd stage (r1) should only indicate not-busy |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | fix issue with priv_mode not being passed correctly... |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | fix issue with d_valid in dcache, was not being set... |
tree | commitdiff |
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