soc.git
2 years agomove IRQLine out because that makes soc dependent on LambdaSOC
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 13:12:36 +0000 (14:12 +0100)]
move IRQLine out because that makes soc dependent on LambdaSOC

2 years ago80 char limit, remove creation of stall from ack/cyc, it has to be
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 11:47:24 +0000 (12:47 +0100)]
80 char limit, remove creation of stall from ack/cyc, it has to be
done in the parent because that is what knows the usage

2 years agowb_async: Allow different feature fields for master/slave busses
Raptor Engineering Development Team [Thu, 14 Apr 2022 00:57:20 +0000 (19:57 -0500)]
wb_async: Allow different feature fields for master/slave busses

2 years agoAdd separate memory clock register to SYSCON
Raptor Engineering Development Team [Thu, 14 Apr 2022 00:56:47 +0000 (19:56 -0500)]
Add separate memory clock register to SYSCON

2 years agoissuer.py: add microwatt_old and microwatt_debug options
Tobias Platen [Tue, 12 Apr 2022 18:37:00 +0000 (20:37 +0200)]
issuer.py: add microwatt_old and microwatt_debug options

2 years agoSeparate core and nest clocks in Microwatt SYSCON
Raptor Engineering Development Team [Mon, 11 Apr 2022 19:31:02 +0000 (14:31 -0500)]
Separate core and nest clocks in Microwatt SYSCON

2 years agoAdd initial wrapper for Wishbone asynchronous bridge module
Raptor Engineering Development Team [Mon, 11 Apr 2022 19:30:39 +0000 (14:30 -0500)]
Add initial wrapper for Wishbone asynchronous bridge module

2 years agoBegin a formal proof of the LVT-based 1W/1R wrapper
Cesar Strauss [Sun, 10 Apr 2022 15:21:14 +0000 (12:21 -0300)]
Begin a formal proof of the LVT-based 1W/1R wrapper

Start with a Bounded Model Check, on the transparent case.

2 years agoImplement 1W/1R with a transparent (or not) read port.
Cesar Strauss [Sun, 10 Apr 2022 12:24:19 +0000 (09:24 -0300)]
Implement 1W/1R with a transparent (or not) read port.

Seems that it's just a matter of the underlying memories being
transparent (or not).

2 years agoImplement a true 1W/1R memory from 1RW blocks
Cesar Strauss [Sat, 9 Apr 2022 21:15:52 +0000 (18:15 -0300)]
Implement a true 1W/1R memory from 1RW blocks

Uses four phased memories, multiplexers, and FFRAM for the LVT.
Only non-transparent reads, for now.
Test case is included, seems to work.

2 years agoadd a new make target for setting coldboot firmware at 0xfff0_0000
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 12:36:12 +0000 (13:36 +0100)]
add a new make target for setting coldboot firmware at 0xfff0_0000
put reset values of pc and msr into Issuer explicitly on reset

2 years agosyntax error
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:10:19 +0000 (21:10 +0100)]
syntax error

2 years agoadd dram to SysCon
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:10:00 +0000 (21:10 +0100)]
add dram to SysCon

2 years agoadd SPI offset to microwatt syscon
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 17:41:30 +0000 (18:41 +0100)]
add SPI offset to microwatt syscon

2 years agoonly add clock-settings on ECP5 due to special SPI clock handling
Luke Kenneth Casson Leighton [Wed, 6 Apr 2022 11:29:03 +0000 (12:29 +0100)]
only add clock-settings on ECP5 due to special SPI clock handling
(Tercel QSPI)

2 years agoadd tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 21:32:32 +0000 (22:32 +0100)]
add tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8

2 years agodisable sphinx verilg-diagrams for now
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 20:41:51 +0000 (21:41 +0100)]
disable sphinx verilg-diagrams for now

2 years agoallow direction-setting on each of dq0-3 in Tercel QSPI
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 19:13:41 +0000 (20:13 +0100)]
allow direction-setting on each of dq0-3 in Tercel QSPI

2 years agocant stand the practice of putting docstrings *after* the code they
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 23:52:27 +0000 (00:52 +0100)]
cant stand the practice of putting docstrings *after* the code they
document.  a trick to get them to go on one line: semi-colons

2 years agoExtend the proof to a non-transparent port
Cesar Strauss [Sun, 3 Apr 2022 22:12:15 +0000 (19:12 -0300)]
Extend the proof to a non-transparent port

For the non-transparent case, have to distinguish the case of a
simultaneous write, where the expected value is the previous
value of the holding register, not the new.

2 years agoRun formal proof on both types (even/odd) of phased SRAMs
Cesar Strauss [Sun, 3 Apr 2022 19:31:13 +0000 (16:31 -0300)]
Run formal proof on both types (even/odd) of phased SRAMs

2 years agoComplete the formal proof of the pseudo dual port SRAM
Cesar Strauss [Sun, 3 Apr 2022 19:10:16 +0000 (16:10 -0300)]
Complete the formal proof of the pseudo dual port SRAM

Have to ensure that the holding register is in sync with the memory
contents, to avoid false positives due to unreachable states.

Since we are adding assertions, we can only strengthen the proof, even
if it does become more complex.

2 years agoImplement a debug port on the pseudo 1W/1R SRAM
Cesar Strauss [Sun, 3 Apr 2022 18:50:43 +0000 (15:50 -0300)]
Implement a debug port on the pseudo 1W/1R SRAM

Exposes the debug ports of the underlying memories.
This is needed to assist the induction proof.

2 years agoFormal proof of the phased write dual port memory wrapper
Cesar Strauss [Sun, 3 Apr 2022 18:24:16 +0000 (15:24 -0300)]
Formal proof of the phased write dual port memory wrapper

Similar to the proof of the 1RW memory block, but read and writes are
done on dedicated ports.
For now, only transparent regfile is tested.
To complete the formal verification, an induction proof will follow.

2 years agocorrect default to zero string not zero int
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 16:00:18 +0000 (17:00 +0100)]
correct default to zero string not zero int

2 years agoadd alternative pc_reset argument to issuer_verilog.py
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:30:44 +0000 (11:30 +0100)]
add alternative pc_reset argument to issuer_verilog.py
which propagates right the way down to core.py
next to msr_reset it is now possible to set the pc_reset value.
these actually have to go into the regfile as initial values,
which will be fun for an ASIC

2 years agofix some of instantiation errors in opencores_ethmac.py
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:29:33 +0000 (11:29 +0100)]
fix some of instantiation errors in opencores_ethmac.py

2 years agoFix opencores EthMAC module wiring
Raptor Engineering Development Team [Sat, 2 Apr 2022 21:52:49 +0000 (16:52 -0500)]
Fix opencores EthMAC module wiring

2 years agoImplement transparent read ports on the phased write SRAM
Cesar Strauss [Sat, 2 Apr 2022 20:46:29 +0000 (17:46 -0300)]
Implement transparent read ports on the phased write SRAM

Add a multiplexer to select the write memory instead of the read
memory, in case both port addresses coincide.

2 years agoImplement and test a "phased write port" memory
Cesar Strauss [Fri, 1 Apr 2022 09:47:01 +0000 (06:47 -0300)]
Implement and test a "phased write port" memory

It has one read and one write port, but the writes can only happen every
two cycles.
It uses two 1RW memory blocks.
For the moment, it's not transparent: a simultaneous read and write from
the same address returns the old value. Next step is implementing a
transparent read port.

2 years agoinvert cs_n pin in Tercel
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:44:24 +0000 (14:44 +0100)]
invert cs_n pin in Tercel

2 years agonope, default features in Tercel WB Buses need to not set err yet
Luke Kenneth Casson Leighton [Wed, 30 Mar 2022 09:27:44 +0000 (10:27 +0100)]
nope, default features in Tercel WB Buses need to not set err yet

2 years agoadd bus.err to list of default Wishbone signals in Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:10 +0000 (20:43 +0100)]
add bus.err to list of default Wishbone signals in Tercel

2 years agobyte-reverse Tercel read/write data and config bus. urr...
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 18:54:40 +0000 (19:54 +0100)]
byte-reverse Tercel read/write data and config bus. urr...

2 years agoset clock freq Constant length to 32-bit in Tercel.
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 18:18:07 +0000 (19:18 +0100)]
set clock freq Constant length to 32-bit in Tercel.
this really needs to come from SYSCON

2 years agoself.specials does not exist, Instances must be added as submodules
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 14:28:52 +0000 (15:28 +0100)]
self.specials does not exist, Instances must be added as submodules

2 years agomore sorting out wishbone names in Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 13:33:49 +0000 (14:33 +0100)]
more sorting out wishbone names in Tercel

2 years agofix names of Instance signals in Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 13:15:00 +0000 (14:15 +0100)]
fix names of Instance signals in Tercel
names *start* with o_ for output i_ for input p_ for parameter a_ for attr
not end with them

2 years agosort out variable names in Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 13:10:30 +0000 (14:10 +0100)]
sort out variable names in Tercel

2 years agoself.comb does not exist, comb is a local temp-var (comb = m.d.comb)
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:51:49 +0000 (13:51 +0100)]
self.comb does not exist, comb is a local temp-var (comb = m.d.comb)

2 years agowhitespace cleanup (80 char limit)
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:11:47 +0000 (13:11 +0100)]
whitespace cleanup (80 char limit)

2 years agoAdd initial integration for OpenCores 10/100 Ethernet MAC
Raptor Engineering Development Team [Tue, 29 Mar 2022 01:11:17 +0000 (20:11 -0500)]
Add initial integration for OpenCores 10/100 Ethernet MAC

2 years agoFinish the SRAM formal proof by implementing induction
Cesar Strauss [Sun, 27 Mar 2022 17:23:39 +0000 (14:23 -0300)]
Finish the SRAM formal proof by implementing induction

Add a combinatorial (no delay) debug read port to the SRAM model,
for turning an unreacheable state (memory and holding register differ)
into an illegal state.
Just two clock cycles are needed for a working proof.

2 years agoAdd formal verification of the single port memory block
Cesar Strauss [Sat, 26 Mar 2022 21:09:12 +0000 (18:09 -0300)]
Add formal verification of the single port memory block

We test a single, random memory location.
If any memory location, chosen at random, passes, then the whole memory
is correct.
Note that an induction proof is still missing, since it requires
additional assertions to avoid illegal states.

2 years agorename PLRU modules to avoid conflict in microwatt
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 20:18:53 +0000 (20:18 +0000)]
rename PLRU modules to avoid conflict in microwatt

2 years agowhitespace cleanup (80 char limit, pep8)
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 10:45:59 +0000 (10:45 +0000)]
whitespace cleanup (80 char limit, pep8)

2 years agoturn CompALU/CompLDST latches synchronous
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 10:00:13 +0000 (10:00 +0000)]
turn CompALU/CompLDST latches synchronous
to cut down combinatorial loops

2 years agoAdd initial Tercel integration
Raptor Engineering Development Team [Mon, 14 Mar 2022 00:33:04 +0000 (19:33 -0500)]
Add initial Tercel integration

NOTE: Still needs testing on physical hardware,
waiting for Arctic Tern support.

2 years agoSimulate some read/write/modify operations on the SRAM model
Cesar Strauss [Sun, 13 Mar 2022 19:13:04 +0000 (16:13 -0300)]
Simulate some read/write/modify operations on the SRAM model

2 years agoAdd a Single R/W Port SRAM model
Cesar Strauss [Sun, 13 Mar 2022 11:56:24 +0000 (08:56 -0300)]
Add a Single R/W Port SRAM model

Begin making unit tests by checking with Yosys.

2 years agoadd extra pipeline stages to ALU FU to make timing
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 16:08:29 +0000 (16:08 +0000)]
add extra pipeline stages to ALU FU to make timing

2 years agointroduce extra register of delay to split combinatorial loops
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 15:45:16 +0000 (15:45 +0000)]
introduce extra register of delay to split combinatorial loops
by making fetch_ic_i_valid sync

2 years agoRevert "read last row from r.wb.adr not r.req_adr in icache"
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 14:43:19 +0000 (14:43 +0000)]
Revert "read last row from r.wb.adr not r.req_adr in icache"

This reverts commit 1bcb90676398c8fa0c309c3c7ed3c9ef306c577e.

2 years agoRevert "store cur_state.pc+4 in separate register to help reduce"
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 14:13:15 +0000 (14:13 +0000)]
Revert "store cur_state.pc+4 in separate register to help reduce"

This reverts commit d9b58d594ede33db2b0290d7edf8e062f5e91460.

2 years agostore cur_state.pc+4 in separate register to help reduce
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 13:22:39 +0000 (13:22 +0000)]
store cur_state.pc+4 in separate register to help reduce
combinatorial chains

2 years agoread last row from r.wb.adr not r.req_adr in icache
Luke Kenneth Casson Leighton [Sat, 12 Mar 2022 13:22:15 +0000 (13:22 +0000)]
read last row from r.wb.adr not r.req_adr in icache

2 years agoremove stbs_done in icache.py
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 16:47:27 +0000 (16:47 +0000)]
remove stbs_done in icache.py

2 years agoremove ld_stbs_done from dcache: not needed
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 15:46:15 +0000 (15:46 +0000)]
remove ld_stbs_done from dcache: not needed

2 years agowork-in-progress on sdram opencores wrapper
Luke Kenneth Casson Leighton [Tue, 8 Mar 2022 15:45:49 +0000 (15:45 +0000)]
work-in-progress on sdram opencores wrapper

2 years agoCopy the startup delay from issuer.py to inorder.py
Cesar Strauss [Sun, 6 Mar 2022 18:00:37 +0000 (15:00 -0300)]
Copy the startup delay from issuer.py to inorder.py

Fixes TestIssuerInternalInOrder hanging at startup.

2 years agoattempting to introduce an extra few clock cycles delay on power-up
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:43:39 +0000 (17:43 +0000)]
attempting to introduce an extra few clock cycles delay on power-up
this may help with initialisation of I-Cache SRAM which is combinatorial.
maybe

2 years agofor lulz make I-Cache possible to set to 32-bit (XLEN=32)
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 21:23:12 +0000 (21:23 +0000)]
for lulz make I-Cache possible to set to 32-bit (XLEN=32)

2 years agobit_length is 1 more than needed: subtract 1 from XLEN first
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:50:33 +0000 (19:50 +0000)]
bit_length is 1 more than needed: subtract 1 from XLEN first

2 years agofix up shift_rot test_pipe_caller to new regspeckls style
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:34:05 +0000 (19:34 +0000)]
fix up shift_rot test_pipe_caller to new regspeckls style

2 years agoconvert shift_rot pipeline to XLEN=32/64
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:25:54 +0000 (19:25 +0000)]
convert shift_rot pipeline to XLEN=32/64

2 years agofix up Logical pipeline to produce HDL with XLEN=32
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 19:16:35 +0000 (19:16 +0000)]
fix up Logical pipeline to produce HDL with XLEN=32
fix Logical test_pipe_caller.py to use new regspeckls style

2 years agowhoops ALU common output target must be XLEN-bit,
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:48:28 +0000 (18:48 +0000)]
whoops ALU common output target must be XLEN-bit,
cannot set to length of output (o) using Signal.like

2 years agoset up dummy parent_pspec to pass XLEN=64 in
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:41:43 +0000 (18:41 +0000)]
set up dummy parent_pspec to pass XLEN=64 in
ALU test_pipe_spec.py

2 years agostart on converting MUL and DIV pipelines to XLEN
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:37:37 +0000 (18:37 +0000)]
start on converting MUL and DIV pipelines to XLEN

2 years agoconvert from public static functions/properties for regspecs
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:17:08 +0000 (18:17 +0000)]
convert from public static functions/properties for regspecs
to member functions to obtain regspecs
this allows pspec (containing XLEN) to be passed to the regspecs,
which in turn allows them to be dynamically set by issuer_verilog.py
and unit tests

2 years agofix ALU with XLEN=32, carry and overflow
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:09:13 +0000 (18:09 +0000)]
fix ALU with XLEN=32, carry and overflow

2 years agouse XLEN in Function Units (starting with ALU)
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 18:01:54 +0000 (18:01 +0000)]
use XLEN in Function Units (starting with ALU)

2 years agoadd XLEN to issuer_verilog.py defaults to 64
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 17:31:51 +0000 (17:31 +0000)]
add XLEN to issuer_verilog.py defaults to 64

2 years agoadd XLEN option to regfiles via pspec
Luke Kenneth Casson Leighton [Sun, 27 Feb 2022 17:17:07 +0000 (17:17 +0000)]
add XLEN option to regfiles via pspec

2 years agoadd running instructions
Jacob Lifshay [Thu, 24 Feb 2022 03:33:13 +0000 (19:33 -0800)]
add running instructions

2 years agoadd formal proof for shift/rot o.ok
Jacob Lifshay [Thu, 24 Feb 2022 03:28:02 +0000 (19:28 -0800)]
add formal proof for shift/rot o.ok

2 years agoclean up code
Jacob Lifshay [Thu, 24 Feb 2022 03:16:17 +0000 (19:16 -0800)]
clean up code

2 years agoadd formal proof for OP_RLCR
Jacob Lifshay [Thu, 24 Feb 2022 03:12:49 +0000 (19:12 -0800)]
add formal proof for OP_RLCR

2 years agoadd formal proof for OP_RLCL
Jacob Lifshay [Thu, 24 Feb 2022 03:01:49 +0000 (19:01 -0800)]
add formal proof for OP_RLCL

2 years agoadd formal proof for OP_RLC
Jacob Lifshay [Thu, 24 Feb 2022 02:40:48 +0000 (18:40 -0800)]
add formal proof for OP_RLC

2 years agoforgot to pass cix (cache-inhibited) through to LD/ST which was
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 17:17:50 +0000 (17:17 +0000)]
forgot to pass cix (cache-inhibited) through to LD/ST which was
causing D-Cache to make too many read/writes and overrun wishbone
bus addressing on peripherals.
D-Cache always (for non-cache-inhibited) makes 8 64-bit requests:
if a memory-mapped peripheral has only say 3 32-bit CSRs then the
additional requests beyond the range of the peripheral will cause
a permanent lock-up

2 years agospeed up shift/rot formal proof by running stuff in parallel
Jacob Lifshay [Tue, 22 Feb 2022 09:33:16 +0000 (01:33 -0800)]
speed up shift/rot formal proof by running stuff in parallel

it now runs in about 1m30s in `pytest -n auto <file>.py`

also start work on rewriting proofs to hopefully work better, all
of grev, ternlog, extswsli, shl, and shr are completed.

2 years agoagain reduce combinatorial chains, similar to Trap pipeline,
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 00:26:14 +0000 (00:26 +0000)]
again reduce combinatorial chains, similar to Trap pipeline,
introduce dummy passthrough stage in Branch pipeline

2 years agoadd syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:58:58 +0000 (23:58 +0000)]
add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again

2 years agosame as shiftrot, split out separate pipelines for logical
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:51:32 +0000 (23:51 +0000)]
same as shiftrot, split out separate pipelines for logical
stages in order to meet FPGA timing

2 years agoput LDST go-store on a 1-clock delay to help with combinatorial chains
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:38:13 +0000 (23:38 +0000)]
put LDST go-store on a 1-clock delay to help with combinatorial chains

2 years agoname core_stop and terminated_o synchronous to potentially help
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 23:28:50 +0000 (23:28 +0000)]
name core_stop and terminated_o synchronous to potentially help
cut down on combinatorial chains

2 years agonope, it's perfectly fine
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:20:21 +0000 (22:20 +0000)]
nope, it's perfectly fine

Revert "weird exception, oe not found in the shiftrot input record"

This reverts commit 264cc7fd7d7547e1e19424b8f8fd0fbfea29cec5.

2 years agoweird exception, oe not found in the shiftrot input record
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:17:18 +0000 (22:17 +0000)]
weird exception, oe not found in the shiftrot input record

Revert "separate out shiftrot stages due to size of main stage being so large"

This reverts commit 87d6b84e96fb62cda16cc9f335e34fe15ad6cd97.

2 years agoseparate out shiftrot stages due to size of main stage being so large
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 22:09:42 +0000 (22:09 +0000)]
separate out shiftrot stages due to size of main stage being so large

2 years agoadd blockram style to regfile Memory
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:50:22 +0000 (20:50 +0000)]
add blockram style to regfile Memory

2 years agouse block_ram attribute for FPGA synthesis
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 20:49:36 +0000 (20:49 +0000)]
use block_ram attribute for FPGA synthesis

2 years agoreduce number of d-cache lines in microwatt fpga mode
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)]
reduce number of d-cache lines in microwatt fpga mode

2 years agocouple of adjustments to reduce gate count in i/d-cache
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:41:42 +0000 (19:41 +0000)]
couple of adjustments to reduce gate count in i/d-cache

2 years agoadd SDRAM Configuration Record
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 19:41:23 +0000 (19:41 +0000)]
add SDRAM Configuration Record

2 years agoreduce TLB set size from 64 to 16 to get FPGA resource utilisation down
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:53:06 +0000 (11:53 +0000)]
reduce TLB set size from 64 to 16 to get FPGA resource utilisation down

2 years agodrastically reduce I-Cache size in microwatt-compat mode
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:41:29 +0000 (11:41 +0000)]
drastically reduce I-Cache size in microwatt-compat mode
should really be called "small FPGA mode" or something

2 years agoparameterise I-Cache similar to D-Cache. lots of "self."
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 11:36:19 +0000 (11:36 +0000)]
parameterise I-Cache similar to D-Cache. lots of "self."
all over the place. yuk.

2 years agoadd grev
Jacob Lifshay [Fri, 18 Feb 2022 06:01:41 +0000 (22:01 -0800)]
add grev

2 years agoadd opencores SDRAM verilog wrapper
Luke Kenneth Casson Leighton [Thu, 17 Feb 2022 17:09:21 +0000 (17:09 +0000)]
add opencores SDRAM verilog wrapper