| 2022-02-18 |
Luke Kenneth Casson... | reduce TLB set size from 64 to 16 to get FPGA resource...
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | drastically reduce I-Cache size in microwatt-compat...
|
commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | parameterise I-Cache similar to D-Cache. lots of "self."
|
commit | commitdiff | tree |
| 2022-02-17 |
Luke Kenneth Casson... | add opencores SDRAM verilog wrapper
|
commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | oof. big update to DCache to accept config parameters
|
commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | connect UART16550 pins if given
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | for *write* the counter-address on downconvert was...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add wishbone downconvert "skip" of slave sel so that...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add SysCon reg_info, has uart and has large SYSCON
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | sigh, stall was not working but actually turns out...
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add option to specify UART16550 width (32/8)
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add beginnings of syscon bus peripheral
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | update comments
|
commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | resolve WBDownConvert ack issues when stall is active
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | strip first 3 bits of WB address from microwatt d/i...
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | slave sends stall signal, master receives, in
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | sort out ExternalCore signal names
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add wishbone slave signal to downconvert if present
|
commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add external core verilog wrapper, ironically around...
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | bugfixing for ls2 imports of uart16550
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "remove dummy trap pipeline"
|
commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "doh"
|
commit | commitdiff | tree |
| 2022-02-09 |
Luke Kenneth Casson... | add opencores uart16550 instance wrapper
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | fix bug in itlb_valid SRLatch set/reset, a bit weird...
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | whoops tlb_valids in ICache is a combinatorial-get/set
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | convert TLBValidArray in ICache to SRLatch
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | add microwatt external core build target to Makefile
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use an SRLatch for cache_valids, at least it reduces...
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache tags in dcache
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache_tags in icache
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | doh
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove dummy trap pipeline
|
commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove combinatorial loop from MultiCompUnit
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | break out cache_tags and cache_valids (again) this...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove CacheTagArray in icache.py
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | create Memory for Cache Tags in I-Cache
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove unneeded parameter
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | add Array of CacheValids back in, so as to reduce LUT4...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | tagset is a local Signal in ICache
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | identify combinatorial loop signals in MultiCompUnit...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | use nmigen Memory in I-Cache for TLB Lookups
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | put itlb_valid back, ready for conversion to Memory...
|
commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | convert CacheRAM to Memory, acts much faster now
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | explanatory comment when page hit is the same for stores
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | use right offset in dcache wb address
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | re-examining dcache.vhdl, still did not get the store...
|
commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | bug in dcache.py where when two stores occur in the...
|
commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | in LoadStore1 capture the address for misaligned dual...
|
commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | sort out misaligned store in LoadStore1
|
commit | commitdiff | tree |
| 2022-01-27 |
Luke Kenneth Casson... | for second aligned request truncate address to nearest...
|
commit | commitdiff | tree |
| 2022-01-25 |
Luke Kenneth Casson... | add license and copyright header to dcache.py,
|
commit | commitdiff | tree |
| 2022-01-25 |
Luke Kenneth Casson... | LDSTException now passing bits of SRR1 around to the...
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | hmm there seems to have been an error in DTLB Read,
|
commit | commitdiff | tree |
| 2022-01-24 |
Luke Kenneth Casson... | bool test on traptype to
|
commit | commitdiff | tree |
| 2022-01-23 |
Luke Kenneth Casson... | looked in soc.vhdl in microwatt and the parameters...
|
commit | commitdiff | tree |
| 2022-01-23 |
Luke Kenneth Casson... | add debug output of whether stall occurs on dcache
|
commit | commitdiff | tree |
| 2022-01-22 |
Luke Kenneth Casson... | missed setting of r0_full to zero in dcache. not encountered as
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | skip ilang data in branch test_pipe_caller.py
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | attempting to get compunit and test_pipe_caller unit...
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | sigh, monitor DEC/TB StateRegs "properly" so that the...
|
commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | whoops fix bug in setting of DEC/TB (State) in test_core.py
|
commit | commitdiff | tree |
| 2022-01-20 |
Luke Kenneth Casson... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
|
commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | whoops forgot to enable fast-reg read in DMI
|
commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | ISI (0x400) trap is the only one that puts memory-based...
|
commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | move DEC and TB into StateRegs, to make room in FastRegs
|
commit | commitdiff | tree |
| 2022-01-18 |
Luke Kenneth Casson... | add support for DMI debug read of FAST Regfile SPRs
|
commit | commitdiff | tree |
| 2022-01-18 |
Luke Kenneth Casson... | comments on SRR1 in trap
|
commit | commitdiff | tree |
| 2022-01-18 |
Luke Kenneth Casson... | preserve bits of SRR1 on a TRAP (including all interrupts...
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | fix hrfid and mtmsrd so that it is identical to microwatt
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | connect up DEC/TB FSM pauser from core to Issuer
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | add pause_dec_tb signal (not very sophisticated) to...
|
commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | add signal for pausing the DEC/TB FSM to IssuerBase
|
commit | commitdiff | tree |
| 2022-01-16 |
Luke Kenneth Casson... | raise interrupt on misaligned atomic LDST
|
commit | commitdiff | tree |
| 2022-01-16 |
Luke Kenneth Casson... | pass over store_done correctly from dcache over PortInterface
|
commit | commitdiff | tree |
| 2022-01-16 |
Luke Kenneth Casson... | add CR0 to LDSTCompUnit, for reporting if LR/SC store...
|
commit | commitdiff | tree |
| 2022-01-16 |
Luke Kenneth Casson... | remove PortInterface mmu_done signal,
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | forgot name on dcache Reservation
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | pass over atomic signals to dcache from loadstore.
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | try using req.op in RELOAD_WAIT_ACK to detect whether...
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | pass atomic reserve through from PortInterface to DCache
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | add atomic LR/SC signal to LDSTCompUnit
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | add reserve (atomic) signal to LDST data structures...
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | tidyup PortInterface
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | workaround for bug in dcache where the r1.req waiting...
|
commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | enable both linux-5.7 tests
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | split out CacheTag Record to separate structure
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | update how d_valid is handled
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | missed setting r1.store_way and r1.store_row in STORE_WAIT_A...
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | Revert "dcache 2nd stage (r1) should only indicate...
|
commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | second test for linux-5.7
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | add allow-overlap option to issuer_verilog.py
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | dcache 2nd stage (r1) should only indicate not-busy
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with priv_mode not being passed correctly...
|
commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with d_valid in dcache, was not being set...
|
commit | commitdiff | tree |
| 2022-01-10 |
Luke Kenneth Casson... | LoadStore1 priv_mode was not being correctly picked...
|
commit | commitdiff | tree |
| 2022-01-09 |
Luke Kenneth Casson... | grab the LDST request address for microwatt verilator...
|
commit | commitdiff | tree |
| next |
projects / soc.git / search