soc.git
2 years agoresolve WBDownConvert ack issues when stall is active
Luke Kenneth Casson Leighton [Tue, 15 Feb 2022 01:35:06 +0000 (01:35 +0000)]
resolve WBDownConvert ack issues when stall is active

2 years agostrip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:22:48 +0000 (14:22 +0000)]
strip first 3 bits of WB address from microwatt d/i-bus, bug in microwatt

2 years agoslave sends stall signal, master receives, in
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:22:14 +0000 (14:22 +0000)]
slave sends stall signal, master receives, in
WBDownConvert

2 years agosort out ExternalCore signal names
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:02:59 +0000 (14:02 +0000)]
sort out ExternalCore signal names

2 years agoadd wishbone slave signal to downconvert if present
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 14:02:40 +0000 (14:02 +0000)]
add wishbone slave signal to downconvert if present

2 years agoadd external core verilog wrapper, ironically around Libre-SOC
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 13:08:56 +0000 (13:08 +0000)]
add external core verilog wrapper, ironically around Libre-SOC
(as well as Microwatt)

2 years agobugfixing for ls2 imports of uart16550
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:24:58 +0000 (14:24 +0000)]
bugfixing for ls2 imports of uart16550

2 years agoRevert "remove dummy trap pipeline"
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 18:06:20 +0000 (18:06 +0000)]
Revert "remove dummy trap pipeline"

This reverts commit de3765400532be229ed4dd8a1d9fdcf1b4bca0ef.

2 years agoRevert "doh"
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 18:06:10 +0000 (18:06 +0000)]
Revert "doh"

This reverts commit 26fdc967b91945d102c4efceaba18cfb1506b08a.

2 years agoAdded optional reverse arg to send TDI data MSB-first
Andrey Miroshnikov [Thu, 10 Feb 2022 15:50:20 +0000 (15:50 +0000)]
Added optional reverse arg to send TDI data MSB-first

2 years agoadd opencores uart16550 instance wrapper
Luke Kenneth Casson Leighton [Wed, 9 Feb 2022 12:22:37 +0000 (12:22 +0000)]
add opencores uart16550 instance wrapper

2 years agocorrect path for make target microwatt_external_core
Tobias Platen [Tue, 1 Feb 2022 18:13:33 +0000 (18:13 +0000)]
correct path for make target microwatt_external_core

2 years agofix bug in itlb_valid SRLatch set/reset, a bit weird but it works
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 20:38:45 +0000 (20:38 +0000)]
fix bug in itlb_valid SRLatch set/reset, a bit weird but it works

2 years agowhoops tlb_valids in ICache is a combinatorial-get/set
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 16:09:12 +0000 (16:09 +0000)]
whoops tlb_valids in ICache is a combinatorial-get/set
set SRLatch sync=False

2 years agoconvert TLBValidArray in ICache to SRLatch
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:57:56 +0000 (15:57 +0000)]
convert TLBValidArray in ICache to SRLatch

2 years agoadd microwatt external core build target to Makefile
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:47:06 +0000 (15:47 +0000)]
add microwatt external core build target to Makefile

2 years agouse an SRLatch for cache_valids, at least it reduces graphviz size
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:29:44 +0000 (15:29 +0000)]
use an SRLatch for cache_valids, at least it reduces graphviz size

2 years agouse Memory for cache tags in dcache
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:06:56 +0000 (15:06 +0000)]
use Memory for cache tags in dcache

2 years agouse Memory for cache_tags in icache
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:06:36 +0000 (15:06 +0000)]
use Memory for cache_tags in icache

2 years agodoh
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:05:37 +0000 (15:05 +0000)]
doh

2 years agoremove dummy trap pipeline
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 15:02:37 +0000 (15:02 +0000)]
remove dummy trap pipeline

2 years agoremove combinatorial loop from MultiCompUnit
Luke Kenneth Casson Leighton [Mon, 31 Jan 2022 14:59:45 +0000 (14:59 +0000)]
remove combinatorial loop from MultiCompUnit
actually not a loop due to an SRLatch but synth tools still think it is

2 years agobreak out cache_tags and cache_valids (again) this time in dcache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:18:26 +0000 (22:18 +0000)]
break out cache_tags and cache_valids (again) this time in dcache

2 years agoremove CacheTagArray in icache.py
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:08:38 +0000 (22:08 +0000)]
remove CacheTagArray in icache.py

2 years agocreate Memory for Cache Tags in I-Cache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 22:03:24 +0000 (22:03 +0000)]
create Memory for Cache Tags in I-Cache
another huge reduction in number of LUT4s, uses (again) a
combinatorial-read sync-write

2 years agoremove unneeded parameter
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:30:34 +0000 (21:30 +0000)]
remove unneeded parameter

2 years agoadd Array of CacheValids back in, so as to reduce LUT4 usage
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:28:52 +0000 (21:28 +0000)]
add Array of CacheValids back in, so as to reduce LUT4 usage

2 years agotagset is a local Signal in ICache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:11:09 +0000 (21:11 +0000)]
tagset is a local Signal in ICache

2 years agoidentify combinatorial loop signals in MultiCompUnit, TODO resolve
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 21:10:55 +0000 (21:10 +0000)]
identify combinatorial loop signals in MultiCompUnit, TODO resolve

2 years agouse nmigen Memory in I-Cache for TLB Lookups
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 18:16:37 +0000 (18:16 +0000)]
use nmigen Memory in I-Cache for TLB Lookups
surprisingly this makes the Libre-SOC core *50% faster* than microwatt
when running under verilator, despite only being a FSM

2 years agoput itlb_valid back, ready for conversion to Memory, in ICache
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 17:49:17 +0000 (17:49 +0000)]
put itlb_valid back, ready for conversion to Memory, in ICache

2 years agoconvert CacheRAM to Memory, acts much faster now
Luke Kenneth Casson Leighton [Sun, 30 Jan 2022 16:51:41 +0000 (16:51 +0000)]
convert CacheRAM to Memory, acts much faster now

2 years agoexplanatory comment when page hit is the same for stores
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 16:43:56 +0000 (16:43 +0000)]
explanatory comment when page hit is the same for stores

2 years agouse right offset in dcache wb address
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 14:32:23 +0000 (14:32 +0000)]
use right offset in dcache wb address
happened to be the same value but best to be safe, eh?

2 years agore-examining dcache.vhdl, still did not get the store-page
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 13:48:19 +0000 (13:48 +0000)]
re-examining dcache.vhdl, still did not get the store-page
address quite right

2 years agobug in dcache.py where when two stores occur in the same real page
Luke Kenneth Casson Leighton [Sat, 29 Jan 2022 10:17:42 +0000 (10:17 +0000)]
bug in dcache.py where when two stores occur in the same real page
the address is corrupted.

2 years agoin LoadStore1 capture the address for misaligned dual ld/sts in
Luke Kenneth Casson Leighton [Fri, 28 Jan 2022 19:33:13 +0000 (19:33 +0000)]
in LoadStore1 capture the address for misaligned dual ld/sts in
a different way.
something very strange going on with misaligned stores: the address
is advancing far too far under certain circumstances (by 128) which
could just be an MMU / PTE lookup to a different table.

2 years agosort out misaligned store in LoadStore1
Luke Kenneth Casson Leighton [Fri, 28 Jan 2022 03:19:40 +0000 (03:19 +0000)]
sort out misaligned store in LoadStore1

2 years agofor second aligned request truncate address to nearest dword
Luke Kenneth Casson Leighton [Thu, 27 Jan 2022 10:49:14 +0000 (10:49 +0000)]
for second aligned request truncate address to nearest dword
this ensures that DAR gets set correctly if a pagefault 0x300 occurs

2 years agoadd license and copyright header to dcache.py,
Luke Kenneth Casson Leighton [Tue, 25 Jan 2022 00:43:56 +0000 (00:43 +0000)]
add license and copyright header to dcache.py,
extracted authors from git history for the file, but made sure to
credit the original dcache.vhdl as being from microwatt and its
license being CC4

2 years agoLDSTException now passing bits of SRR1 around to the Trap Pipeline
Luke Kenneth Casson Leighton [Tue, 25 Jan 2022 00:42:44 +0000 (00:42 +0000)]
LDSTException now passing bits of SRR1 around to the Trap Pipeline
the actual (former) value of SRR1 is not what is supposed to be used:
the use of the variable "srr1" is a moniker from microwatt

2 years agocomments
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 21:23:49 +0000 (21:23 +0000)]
comments

2 years agohmm there seems to have been an error in DTLB Read,
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 14:11:07 +0000 (14:11 +0000)]
hmm there seems to have been an error in DTLB Read,
where if a write *and* a read occurred at the same time, the old
DTLB-valid entry was given. add similar "forwarding" that is used in
Memory.  DTLB-valid is actually a register not a Memory, where the
DTLB way/tags are a Memory, hence the bug

2 years agobool test on traptype to
Luke Kenneth Casson Leighton [Mon, 24 Jan 2022 11:58:03 +0000 (11:58 +0000)]
bool test on traptype to
ensure two conditions are properly ANDed
also copy correct bits of SRR over, but there is an additional
bug here that needs to be fixed: Exception class needs to pass over
the bottom 16 LSBs of SRR1

2 years agolooked in soc.vhdl in microwatt and the parameters are 64 cache
Luke Kenneth Casson Leighton [Sun, 23 Jan 2022 11:05:23 +0000 (11:05 +0000)]
looked in soc.vhdl in microwatt and the parameters are 64 cache
lines.  this would not be important if it was not explicitly in
the linux-5.7 device-tree file

2 years agoadd debug output of whether stall occurs on dcache
Luke Kenneth Casson Leighton [Sun, 23 Jan 2022 11:04:25 +0000 (11:04 +0000)]
add debug output of whether stall occurs on dcache

2 years agomissed setting of r0_full to zero in dcache. not encountered as
Luke Kenneth Casson Leighton [Sat, 22 Jan 2022 15:19:00 +0000 (15:19 +0000)]
missed setting of r0_full to zero in dcache. not encountered as
a bug but would have done in future

2 years agoskip ilang data in branch test_pipe_caller.py
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 19:26:07 +0000 (19:26 +0000)]
skip ilang data in branch test_pipe_caller.py

2 years agoattempting to get compunit and test_pipe_caller unit tests
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 19:21:57 +0000 (19:21 +0000)]
attempting to get compunit and test_pipe_caller unit tests
up and running again.
grrr

2 years agosigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 00:12:39 +0000 (00:12 +0000)]
sigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
does not end up in a race condition with the SPR pipeline for writing
to DEC or TB

2 years agowhoops fix bug in setting of DEC/TB (State) in test_core.py
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 00:11:53 +0000 (00:11 +0000)]
whoops fix bug in setting of DEC/TB (State) in test_core.py

2 years agowhoops MFSPR DEC/TB was reading from FastRegs not StateRegs
Luke Kenneth Casson Leighton [Thu, 20 Jan 2022 18:38:20 +0000 (18:38 +0000)]
whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
also TBU

2 years agowhoops forgot to enable fast-reg read in DMI
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:46:13 +0000 (17:46 +0000)]
whoops forgot to enable fast-reg read in DMI

2 years agoISI (0x400) trap is the only one that puts memory-based exception
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:18:35 +0000 (17:18 +0000)]
ISI (0x400) trap is the only one that puts memory-based exception
info into SRR1, not *all* memory-based exceptions

2 years agocomments
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:17:40 +0000 (17:17 +0000)]
comments

2 years agomove DEC and TB into StateRegs, to make room in FastRegs
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 12:16:25 +0000 (12:16 +0000)]
move DEC and TB into StateRegs, to make room in FastRegs
also has the advantage that DEC and TB could generate an accurate interrupt

2 years agoadd support for DMI debug read of FAST Regfile SPRs
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 18:15:17 +0000 (18:15 +0000)]
add support for DMI debug read of FAST Regfile SPRs
this to be able to do a side-by-side compare against microwatt
single-stepping

2 years agocomments on SRR1 in trap
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 16:28:49 +0000 (16:28 +0000)]
comments on SRR1 in trap

2 years agopreserve bits of SRR1 on a TRAP (including all interrupts) which in
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 13:42:12 +0000 (13:42 +0000)]
preserve bits of SRR1 on a TRAP (including all interrupts) which in
turn means that PowerDecoder2 has to read SRR1

2 years agofix hrfid and mtmsrd so that it is identical to microwatt
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 18:00:52 +0000 (18:00 +0000)]
fix hrfid and mtmsrd so that it is identical to microwatt
both allow MSR.ME to be set, which walks linux-5.7 along a different
codepath particularly for 0x900 exception handling

2 years agoconnect up DEC/TB FSM pauser from core to Issuer
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 17:59:59 +0000 (17:59 +0000)]
connect up DEC/TB FSM pauser from core to Issuer

2 years agocomments
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 12:01:17 +0000 (12:01 +0000)]
comments

2 years agowhitespace
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 12:00:36 +0000 (12:00 +0000)]
whitespace

2 years agoadd pause_dec_tb signal (not very sophisticated) to Core
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 11:59:56 +0000 (11:59 +0000)]
add pause_dec_tb signal (not very sophisticated) to Core
TODO, detect MTSPR and DEC/TB SPR being written to, but for now just
detect an entire SPR pipeline

2 years agoadd signal for pausing the DEC/TB FSM to IssuerBase
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 11:50:50 +0000 (11:50 +0000)]
add signal for pausing the DEC/TB FSM to IssuerBase
there is a potential issue with the DEC SPR that needs solving,
and there is a race condition where an mtspr DEC/TB could get
overwritten
adding a "pause" mechanism to the FSM should solve that

2 years agoraise interrupt on misaligned atomic LDST
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 16:29:13 +0000 (16:29 +0000)]
raise interrupt on misaligned atomic LDST

2 years agopass over store_done correctly from dcache over PortInterface
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 16:28:49 +0000 (16:28 +0000)]
pass over store_done correctly from dcache over PortInterface
into LDSTCompUnit so that it can set CR0 correctly on stdcx. etc.

2 years agoadd CR0 to LDSTCompUnit, for reporting if LR/SC store is done
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 09:08:52 +0000 (09:08 +0000)]
add CR0 to LDSTCompUnit, for reporting if LR/SC store is done

2 years agoremove PortInterface mmu_done signal,
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 08:54:22 +0000 (08:54 +0000)]
remove PortInterface mmu_done signal,
add store_done

2 years agoforgot name on dcache Reservation
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 21:47:18 +0000 (21:47 +0000)]
forgot name on dcache Reservation

2 years agopass over atomic signals to dcache from loadstore.
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 20:56:35 +0000 (20:56 +0000)]
pass over atomic signals to dcache from loadstore.
does not do everything yet: load-quad for example is not included

2 years agotry using req.op in RELOAD_WAIT_ACK to detect whether request
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 18:44:24 +0000 (18:44 +0000)]
try using req.op in RELOAD_WAIT_ACK to detect whether request
can complete next cycle

2 years agopass atomic reserve through from PortInterface to DCache
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:21:50 +0000 (14:21 +0000)]
pass atomic reserve through from PortInterface to DCache
not yet doing anything with it, so should be fine

2 years agoadd atomic LR/SC signal to LDSTCompUnit
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:06:44 +0000 (14:06 +0000)]
add atomic LR/SC signal to LDSTCompUnit

2 years agoadd reserve (atomic) signal to LDST data structures including PortInterface
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:04:55 +0000 (14:04 +0000)]
add reserve (atomic) signal to LDST data structures including PortInterface

2 years agotidyup PortInterface
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:03:02 +0000 (14:03 +0000)]
tidyup PortInterface

2 years agoworkaround for bug in dcache where the r1.req waiting to be deployed ldst_misalign
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 12:36:52 +0000 (12:36 +0000)]
workaround for bug in dcache where the r1.req waiting to be deployed
was interfering with the current state being executed
http://lists.libre-soc.org/pipermail/libre-soc-dev/2022-January/004358.html

2 years agoenable both linux-5.7 tests
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 12:35:12 +0000 (12:35 +0000)]
enable both linux-5.7 tests

2 years agosplit out CacheTag Record to separate structure
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 14:02:19 +0000 (14:02 +0000)]
split out CacheTag Record to separate structure

2 years agoupdate how d_valid is handled
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 03:02:39 +0000 (03:02 +0000)]
update how d_valid is handled

2 years agomissed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:42:07 +0000 (01:42 +0000)]
missed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state

2 years agoRevert "dcache 2nd stage (r1) should only indicate not-busy"
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:28:17 +0000 (01:28 +0000)]
Revert "dcache 2nd stage (r1) should only indicate not-busy"

This reverts commit a03aefb1e8ae7d6110a328b57f1336890ebee469.

2 years agosecond test for linux-5.7
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:27:09 +0000 (01:27 +0000)]
second test for linux-5.7

2 years agoadd allow-overlap option to issuer_verilog.py
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 20:09:03 +0000 (20:09 +0000)]
add allow-overlap option to issuer_verilog.py

2 years agodcache 2nd stage (r1) should only indicate not-busy
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 12:11:12 +0000 (12:11 +0000)]
dcache 2nd stage (r1) should only indicate not-busy
(r1.full) when all the ACKs of a cache-line fill have been processed
doing this too early results in r0 being pushed into r1 whilst
ACKs are still outstanding, and their completion corrupts the
operation that should not have been put into r1 in the first place

2 years agofix issue with priv_mode not being passed correctly to MMU
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 11:22:24 +0000 (11:22 +0000)]
fix issue with priv_mode not being passed correctly to MMU
on instruction load

2 years agofix issue with d_valid in dcache, was not being set properly
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 11:21:40 +0000 (11:21 +0000)]
fix issue with d_valid in dcache, was not being set properly

2 years agoLoadStore1 priv_mode was not being correctly picked up by the MMU
Luke Kenneth Casson Leighton [Mon, 10 Jan 2022 23:03:25 +0000 (23:03 +0000)]
LoadStore1 priv_mode was not being correctly picked up by the MMU
priv_mode needs to come from the original LD/ST request (or the
fetch), which was not happening

2 years agograb the LDST request address for microwatt verilator debug purposes
Luke Kenneth Casson Leighton [Sun, 9 Jan 2022 23:40:34 +0000 (23:40 +0000)]
grab the LDST request address for microwatt verilator debug purposes

2 years agoadd linux-5.7 unit test which showed a silly error:
Luke Kenneth Casson Leighton [Sun, 9 Jan 2022 23:29:10 +0000 (23:29 +0000)]
add linux-5.7 unit test which showed a silly error:
LDST requests through PortInterface were truncated to 48 bits,
where linux uses the top 2 bits of an address for VM/guest (Quadrant 0-3)

2 years agofix MMU lookup after 2nd request (misaligned) by also updating the
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 17:46:56 +0000 (17:46 +0000)]
fix MMU lookup after 2nd request (misaligned) by also updating the
ldst_r with the next address/byte_sel

2 years agoadd microwatt mmu.bin test5 to show page-fault on misaligned LD
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 17:27:42 +0000 (17:27 +0000)]
add microwatt mmu.bin test5 to show page-fault on misaligned LD

2 years agodo not clear out ldst request after TLB entry is added
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 16:49:27 +0000 (16:49 +0000)]
do not clear out ldst request after TLB entry is added

2 years agoenable microwatt mmu test2
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:42:58 +0000 (15:42 +0000)]
enable microwatt mmu test2

2 years agowhitespace and use exc is None not exc == None
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:41:32 +0000 (15:41 +0000)]
whitespace and use exc is None not exc == None

2 years agoadd a second LD request to dcache which is merged with first,
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:26:03 +0000 (15:26 +0000)]
add a second LD request to dcache which is merged with first,
to implement mis-aligned LD operations

2 years agostart adding in mis-aligned LD/ST support into LoadStore1
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 14:10:16 +0000 (14:10 +0000)]
start adding in mis-aligned LD/ST support into LoadStore1
currently not activated or used so will have no effect

2 years agoadd function test_pi_ld_misalign
Tobias Platen [Sat, 8 Jan 2022 13:30:25 +0000 (14:30 +0100)]
add function test_pi_ld_misalign

2 years agobegin testcase for misalign
Tobias Platen [Fri, 7 Jan 2022 18:07:43 +0000 (19:07 +0100)]
begin testcase for misalign

2 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 7 Jan 2022 16:59:59 +0000 (16:59 +0000)]
whitespace