riscv-isa-sim.git
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-11 Andrew WatermanImplement new FP encoding
2017-04-08 Andrew WatermanImplement vectored interrupt proposal
2017-04-06 Andrew WatermanAdd --enable-misaligned option for misaligned ld/st...
2017-04-01 Yunsup Leeupdate encoding.h to get PMP updates
2017-04-01 Andrew WatermanUpdate LICENSE copyright date
2017-03-30 Wesley W. Terpstrafdt: move interrupt controller into its own node
2017-03-28 Andrew WatermanSet badaddr=0 on illegal instruction traps
2017-03-28 Andrew WatermanOn EBREAK, set badaddr to pc
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2017-03-25 Andrew WatermanDefault to 2 GiB of memory
2017-03-23 Andrew WatermanRequire little-endian host
2017-03-22 Wesley W. Terpstrariscv: replace rtc device with a real clint implementation
2017-03-22 Wesley W. Terpstrasim: declare cores as interrupt-controllers for clint
2017-03-21 Wesley W. Terpstrabootrom: set a0 to hartid and a1 to dtb before boot
2017-03-21 Wesley W. Terpstraconfigstring: rename variables to dts
2017-03-21 Wesley W. Terpstrariscv: remove dependency on num_cores
2017-03-21 Wesley W. Terpstrabootrom: include compiled dtb
2017-03-21 Wesley W. Terpstrasim: create DTS instead of config string
2017-03-21 Wesley W. Terpstrasim: define emulated CPU clock rate to be 1GHz
2017-03-21 Wesley W. Terpstraautoconf: put location of 'dtc' into config.h
2017-03-21 Palmer Dabbeltspec bump
2017-03-20 Andrew WatermanPUM -> SUM; expose MXR to S-mode
2017-03-16 Andrew WatermanSimplify interrupt-stack discipline
2017-03-13 Andrew WatermanImplement mstatus.TW, mstatus.TVM, and mstatus.TSR
2017-03-07 Andrew WatermanDon't overload illegal instruction trap in interactive...
2017-02-27 Andrew WatermanSv57 and Sv64 are not spec'd yet
2017-02-25 Andrew WatermanNew counter enable scheme
2017-02-25 Tim NewsomeUpdate bits to latest spec.
2017-02-23 Tim NewsomeImplement halt request.
2017-02-22 Tim NewsomeImprove debug performance.
2017-02-22 Tim NewsomeDon't waste time spinning in place in debug mode
2017-02-21 Andrew Watermanserialize simulator on wfi
2017-02-21 Andrew WatermanTake M-mode interrupts over S-mode interrupts
2017-02-21 Andrew Watermanpermit MMIO loads to MSIP bit
2017-02-19 Andrew WatermanMake HW setting of PTE A/D bits optional (by configure...
2017-02-18 Andrew WatermanSpike uarch needs TLB flush after SPTBR write
2017-02-18 Tim NewsomeCompress log output of jump-to-self loops.
2017-02-16 Tim NewsomeRemove noisy debugs.
2017-02-16 Tim NewsomeSet cmderr when data is accessed while busy.
2017-02-16 Tim NewsomeImplement autoexec. DMI op 2 is just write now.
2017-02-15 Tim NewsomeImplement resume (untested).
2017-02-15 Andrew Watermansfence.vm -> sfence.vma
2017-02-14 Tim NewsomeImplement program buffer preexec/postexec.
2017-02-13 Tim Newsomedbus -> dmi
2017-02-13 Tim NewsomeAbstract register read mostly working.
2017-02-12 Tim NewsomeFix stack overflow and support --rbb-port=0
2017-02-11 Tim NewsomeEntering debug mode now jumps to "dynamic rom"
2017-02-10 Tim NewsomeImplement hartstatus field.
2017-02-10 Tim NewsomeRemove gdbserver support.
2017-02-09 Tim NewsomeAdd writable ibuf and data registers.
2017-02-09 Tim NewsomeServe up a correct dmcontrol register.
2017-02-08 Andrew WatermanEncode VM type in sptbr, not mstatus
2017-02-07 Tim NewsomeOpenOCD does a dmi read and gets dummy value back.
2017-02-07 Tim NewsomeMerge pull request #83 from bacam/gdb-protocol-fixes
2017-02-07 Tim NewsomeRemove unnecessary circular buffer code.
2017-02-07 Tim NewsomeRefactor remote bitbang code.
2017-02-03 Tim NewsomeOpenOCD RISC-V code now gets to scan out dtmcontrol.
2017-02-03 Tim NewsomeOpenOCD can now scan out the hacked IDCODE.
2017-02-03 Tim NewsomeOpenOCD connects, and sends some data that we receive.
2017-02-03 Andrew WatermanFix interrupt delegation for coprocessors
2017-02-02 Andrew WatermanFor FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonica...
2017-02-02 Andrew WatermanSet xPIE=1 on xRET
2017-01-08 Andrew WatermanOnly allow SIP.SSIP to be toggled if the interrupt...
2017-01-08 Andrew WatermanMake SIP.STIP read-only
2017-01-06 David CravenComply with GNU coding standards.
2016-12-30 Brian CampbellOnly read exception flag in gdb register read/write...
2016-12-21 Brian CampbellFix gdb communication error (#82)
2016-12-21 Brian CampbellRemove extra gdb protocol responses on register writes
2016-12-21 Brian CampbellFix gdb protocol register read of S0
2016-12-17 Stefan O'RearUse correct format codes for reg_t and size_t
2016-12-16 Tim NewsomeFix single stepping over faulting instructions. (#80)
2016-12-12 Tim NewsomeReuse the ebreak constants in encoding.h.
2016-12-01 Andy WrightAdded comments about the modified Duff's Device in...
2016-11-14 Andrew WatermanFix 32-bit host portability bug
2016-11-12 Ben GamariEnsure that g++ knows it is building a PCH (#75)
2016-11-10 Andrew WatermanAMOs should always return store faults, not load faults
2016-10-31 Tim NewsomeMake reading/writing fpu regs work.
2016-10-31 Tim NewsomeMinor code cleanup.
2016-10-31 Tim NewsomeCheck for exception after register write.
2016-10-28 Tim NewsomeCheck for exception after reading a register.
2016-10-28 Tim NewsomeFix error message.
2016-10-25 Tim NewsomeIncrease gdb receive buffer.
2016-10-10 Andrew WatermanDon't force load trigger timing to After
2016-10-07 Tim NewsomeDon't die when gdb thinks XLEN is 64 but it's 32.
2016-09-30 Tim NewsomeReturn an error to gdb when memory reads fail. (#71)
2016-09-29 Tim NewsomeUpdate trigger behavior. (#70)
2016-09-13 Scott Beamerrestore clang support by fixing printf identifiers
2016-09-10 Andrew Watermanallow MAFDC bits in MISA to be modified
2016-09-06 Tim NewsomeRemove generic debug tests. (#65)
2016-09-02 Andrew WatermanMerge pull request #62 from riscv/trigger
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-09-02 Tim NewsomeRebuild debug ROM because CSR encoding changed.
2016-09-02 Tim NewsomeSupport triggers on TLB misses.
2016-09-01 Tim NewsomeTheoretically support trigger timing.
2016-08-31 Tim NewsomeRename tdata[0-2] to tdata[1-3].
2016-08-31 Tim NewsomeSave/restore tselect. Set dmode.
2016-08-29 Tim NewsomeFix indent.
2016-08-29 Tim NewsomeRename tdata0--tdata2 to tdata1--tdata3.
2016-08-27 Andrew WatermanAdd (degenerate) performance counter facility
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