soc.git
2022-01-31 Luke Kenneth... use an SRLatch for cache_valids, at least it reduces...
2022-01-31 Luke Kenneth... use Memory for cache tags in dcache
2022-01-31 Luke Kenneth... use Memory for cache_tags in icache
2022-01-31 Luke Kenneth... doh
2022-01-31 Luke Kenneth... remove dummy trap pipeline
2022-01-31 Luke Kenneth... remove combinatorial loop from MultiCompUnit
2022-01-30 Luke Kenneth... break out cache_tags and cache_valids (again) this...
2022-01-30 Luke Kenneth... remove CacheTagArray in icache.py
2022-01-30 Luke Kenneth... create Memory for Cache Tags in I-Cache
2022-01-30 Luke Kenneth... remove unneeded parameter
2022-01-30 Luke Kenneth... add Array of CacheValids back in, so as to reduce LUT4...
2022-01-30 Luke Kenneth... tagset is a local Signal in ICache
2022-01-30 Luke Kenneth... identify combinatorial loop signals in MultiCompUnit...
2022-01-30 Luke Kenneth... use nmigen Memory in I-Cache for TLB Lookups
2022-01-30 Luke Kenneth... put itlb_valid back, ready for conversion to Memory...
2022-01-30 Luke Kenneth... convert CacheRAM to Memory, acts much faster now
2022-01-29 Luke Kenneth... explanatory comment when page hit is the same for stores
2022-01-29 Luke Kenneth... use right offset in dcache wb address
2022-01-29 Luke Kenneth... re-examining dcache.vhdl, still did not get the store...
2022-01-29 Luke Kenneth... bug in dcache.py where when two stores occur in the...
2022-01-28 Luke Kenneth... in LoadStore1 capture the address for misaligned dual...
2022-01-28 Luke Kenneth... sort out misaligned store in LoadStore1
2022-01-27 Luke Kenneth... for second aligned request truncate address to nearest...
2022-01-25 Luke Kenneth... add license and copyright header to dcache.py,
2022-01-25 Luke Kenneth... LDSTException now passing bits of SRR1 around to the...
2022-01-24 Luke Kenneth... comments
2022-01-24 Luke Kenneth... hmm there seems to have been an error in DTLB Read,
2022-01-24 Luke Kenneth... bool test on traptype to
2022-01-23 Luke Kenneth... looked in soc.vhdl in microwatt and the parameters...
2022-01-23 Luke Kenneth... add debug output of whether stall occurs on dcache
2022-01-22 Luke Kenneth... missed setting of r0_full to zero in dcache. not encoun...
2022-01-21 Luke Kenneth... skip ilang data in branch test_pipe_caller.py
2022-01-21 Luke Kenneth... attempting to get compunit and test_pipe_caller unit...
2022-01-21 Luke Kenneth... sigh, monitor DEC/TB StateRegs "properly" so that the...
2022-01-21 Luke Kenneth... whoops fix bug in setting of DEC/TB (State) in test_core.py
2022-01-20 Luke Kenneth... whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
2022-01-19 Luke Kenneth... whoops forgot to enable fast-reg read in DMI
2022-01-19 Luke Kenneth... ISI (0x400) trap is the only one that puts memory-based...
2022-01-19 Luke Kenneth... comments
2022-01-19 Luke Kenneth... move DEC and TB into StateRegs, to make room in FastRegs
2022-01-18 Luke Kenneth... add support for DMI debug read of FAST Regfile SPRs
2022-01-18 Luke Kenneth... comments on SRR1 in trap
2022-01-18 Luke Kenneth... preserve bits of SRR1 on a TRAP (including all interrup...
2022-01-17 Luke Kenneth... fix hrfid and mtmsrd so that it is identical to microwatt
2022-01-17 Luke Kenneth... connect up DEC/TB FSM pauser from core to Issuer
2022-01-17 Luke Kenneth... comments
2022-01-17 Luke Kenneth... whitespace
2022-01-17 Luke Kenneth... add pause_dec_tb signal (not very sophisticated) to...
2022-01-17 Luke Kenneth... add signal for pausing the DEC/TB FSM to IssuerBase
2022-01-16 Luke Kenneth... raise interrupt on misaligned atomic LDST
2022-01-16 Luke Kenneth... pass over store_done correctly from dcache over PortInt...
2022-01-16 Luke Kenneth... add CR0 to LDSTCompUnit, for reporting if LR/SC store...
2022-01-16 Luke Kenneth... remove PortInterface mmu_done signal,
2022-01-15 Luke Kenneth... forgot name on dcache Reservation
2022-01-15 Luke Kenneth... pass over atomic signals to dcache from loadstore.
2022-01-15 Luke Kenneth... try using req.op in RELOAD_WAIT_ACK to detect whether...
2022-01-15 Luke Kenneth... pass atomic reserve through from PortInterface to DCache
2022-01-15 Luke Kenneth... add atomic LR/SC signal to LDSTCompUnit
2022-01-15 Luke Kenneth... add reserve (atomic) signal to LDST data structures...
2022-01-15 Luke Kenneth... tidyup PortInterface
2022-01-15 Luke Kenneth... workaround for bug in dcache where the r1.req waiting... ldst_misalign
2022-01-15 Luke Kenneth... enable both linux-5.7 tests
2022-01-14 Luke Kenneth... split out CacheTag Record to separate structure
2022-01-14 Luke Kenneth... update how d_valid is handled
2022-01-14 Luke Kenneth... missed setting r1.store_way and r1.store_row in STORE_W...
2022-01-14 Luke Kenneth... Revert "dcache 2nd stage (r1) should only indicate...
2022-01-14 Luke Kenneth... second test for linux-5.7
2022-01-12 Luke Kenneth... add allow-overlap option to issuer_verilog.py
2022-01-12 Luke Kenneth... dcache 2nd stage (r1) should only indicate not-busy
2022-01-12 Luke Kenneth... fix issue with priv_mode not being passed correctly...
2022-01-12 Luke Kenneth... fix issue with d_valid in dcache, was not being set...
2022-01-10 Luke Kenneth... LoadStore1 priv_mode was not being correctly picked...
2022-01-09 Luke Kenneth... grab the LDST request address for microwatt verilator...
2022-01-09 Luke Kenneth... add linux-5.7 unit test which showed a silly error:
2022-01-08 Luke Kenneth... fix MMU lookup after 2nd request (misaligned) by also...
2022-01-08 Luke Kenneth... add microwatt mmu.bin test5 to show page-fault on misal...
2022-01-08 Luke Kenneth... do not clear out ldst request after TLB entry is added
2022-01-08 Luke Kenneth... enable microwatt mmu test2
2022-01-08 Luke Kenneth... whitespace and use exc is None not exc == None
2022-01-08 Luke Kenneth... add a second LD request to dcache which is merged with...
2022-01-08 Luke Kenneth... start adding in mis-aligned LD/ST support into LoadStore1
2022-01-08 Tobias Platenadd function test_pi_ld_misalign
2022-01-07 Tobias Platenbegin testcase for misalign
2022-01-07 Luke Kenneth... whitespace
2022-01-07 Luke Kenneth... add missing MSRSpec import
2022-01-07 Luke Kenneth... add msr_o to issuer in microwatt_compat mode
2022-01-06 Luke Kenneth... double the number of lines in the L1 D/I-Cache to match...
2022-01-06 Luke Kenneth... add SECOND_REQ state to loadstore.py, not yet implemented
2022-01-05 Luke Kenneth... add easy-to-access debug reporting of instruction and PC
2022-01-05 Luke Kenneth... use microwatt-specific PLRU due to bug in nmutil version
2022-01-04 Luke Kenneth... fix DriverConflict over MSR write in Issuer/Core by...
2022-01-04 Luke Kenneth... remove FetchFSM from TestIssuer (it served its purpose...
2022-01-03 Luke Kenneth... doh, bus-hack was the wrong way round. *output* the...
2022-01-03 Luke Kenneth... sigh, microwatts wishbone bus usage is non-wishbone...
2022-01-03 Luke Kenneth... sigh have to allow external clocks and reset mess even...
2022-01-03 Luke Kenneth... give module appropriate top-level name in microwatt...
2022-01-03 Luke Kenneth... add missing ext_irq signal to testissuer in microwatt...
2022-01-03 Luke Kenneth... adding an extra option to issuer_verilog.py to be able...
2022-01-03 Luke Kenneth... bring external irq out for microwatt-compatible mode...
2022-01-03 Luke Kenneth... stop display of LDSTCompUnit debug info on every cycle
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