Put simif_t declaration in its own file. (#209)
[riscv-isa-sim.git] / riscv / sim.h
2018-05-31 Andy WrightPut simif_t declaration in its own file. (#209)
2018-03-19 Tim NewsomeMerge pull request #182 from riscv/reset_bits
2018-03-16 Tim NewsomeImplement debug havereset bits
2018-03-16 Andrew WatermanMerge branch 'deepsrc-b_fix_issue183'
2018-03-08 Tim NewsomeMerge pull request #177 from riscv/debug_auth
2018-03-06 Prashanth MundkurNarrow the interface used by the processors and memory...
2018-02-27 Tim NewsomeAdd debug module authentication.
2018-02-19 Tim NewsomeMerge pull request #171 from riscv/sysbusbits
2018-02-01 Tim NewsomeAdd --debug-sba option
2018-01-18 Tim NewsomeSupport debug system bus access.
2017-12-18 Tim NewsomeMerge pull request #165 from riscv/small_progbuf
2017-12-11 Tim NewsomeMake progbuf a run-time option.
2017-11-16 Andrew WatermanMerge pull request #156 from p12nGH/noncontiguous_harts
2017-11-15 Gleb GagarinSupport for non-contiguous hartids
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-05-01 Andrew WatermanSet default entry point from ELF
2017-05-01 Andrew WatermanAdd option to set start pc
2017-05-01 Andrew WatermanSupport more flexible main memory allocation
2017-05-01 Andrew WatermanStore both host & target address in soft TLB
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-11 Andrew WatermanImplement new FP encoding
2017-03-22 Wesley W. Terpstrariscv: replace rtc device with a real clint implementation
2017-03-21 Wesley W. Terpstraconfigstring: rename variables to dts
2017-03-21 Wesley W. Terpstrasim: define emulated CPU clock rate to be 1GHz
2017-02-11 Tim NewsomeEntering debug mode now jumps to "dynamic rom"
2017-02-07 Tim NewsomeOpenOCD does a dmi read and gets dummy value back.
2017-02-03 Tim NewsomeOpenOCD connects, and sends some data that we receive.
2016-06-23 Andrew WatermanRemove legacy HTIF; implement HTIF directly
2016-05-23 Tim NewsomeHave Debug memory kind of working again.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeROM -> RAM -> ROM, waiting for debug int.
2016-05-23 Tim NewsomeAdd -H to start halted.
2016-05-23 Tim Newsomegdb can now read spike memory.
2016-05-23 Tim NewsomeListen on a socket for gdb to connect to.
2016-05-02 Andrew WatermanRemove tohost/fromhost registers
2016-05-01 Andrew WatermanRemove SCRs; add padding after config string
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-04-28 Andrew WatermanAdd --dump-config-string flag
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-03-02 Andrew WatermanUse RV config string rather than FDT
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-09-25 Andrew WatermanRefactor memory access code; add MMIO support
2015-08-06 Andrew WatermanMerge pull request #29 from pmundkur/devel
2015-08-06 Prashanth MundkurAdd an option (-l) to display a log of execution in...
2015-06-06 Andrew WatermanMerge pull request #25 from vapier/master
2015-06-05 Mike Frysingeradd an interactive "pc" command
2015-06-05 Mike Frysingerunify interactive core processing
2015-06-04 Andrew WatermanMerge pull request #24 from vapier/master
2015-06-04 Mike Frysingeradd a help screen to interactive mode
2015-06-01 Andrew WatermanUse single, shared real-time counter
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2014-08-15 Christopher CelioAdded PC histogram option.
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-29 Andrew WatermanPass target machine's return code back to OS
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-07-22 Andrew WatermanAdd xspike program
2013-07-13 Andrew WatermanEliminate infinite loop in debug mode
2013-07-13 Andrew WatermanExit cleanly from debug console
2013-04-23 Andrew Watermandestroy htif on simulator termination
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-05-16 Andrew Watermanfix htif interaction with interactive mode
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-08 Yunsup Lee[sim] add while to interactive_until
2010-09-07 Andrew Waterman[sim] fixed bug in msub.d; added ability to print FPRs...
2010-08-10 Andrew Waterman[sim] removed unused elf loader
2010-07-22 Andrew Waterman[pk,sim] first cut of appserver communication link
2010-07-19 Andrew WatermanReorganized directory structure