Separate page faults from physical memory access exceptions
[riscv-isa-sim.git] / riscv / mmu.cc
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2017-03-20 Andrew WatermanPUM -> SUM; expose MXR to S-mode
2017-02-19 Andrew WatermanMake HW setting of PTE A/D bits optional (by configure...
2017-02-08 Andrew WatermanEncode VM type in sptbr, not mstatus
2016-09-02 Andrew WatermanMerge pull request #62 from riscv/trigger
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-09-02 Tim NewsomeSupport triggers on TLB misses.
2016-08-22 Tim NewsomeImplement address and data triggers.
2016-07-12 Andrew WatermanFix page table walker not respecting valid bit
2016-07-06 Andrew WatermanUpdate to new PTE format
2016-05-23 Tim NewsomeTurn off debugging.
2016-05-23 Tim NewsomeIgnore MPRV in Debug Mode.
2016-05-23 Tim Newsomemprv test now breaks like it's supposed to.
2016-05-23 Tim NewsomeFix off-by-two in general read registers.
2016-05-23 Tim NewsomeWalk page tables to translate addresses.
2016-05-23 Tim NewsomeRemove unused code.
2016-05-23 Tim NewsomeHave Debug memory kind of working again.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeCan jump to and execute Debug ROM.
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew Watermansptbr now a holds a PPN, not an address
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-02-04 Andrew WatermanActually refill ITLB on ITLB miss
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-13 Andrew WatermanFix --dc flag
2015-09-25 Andrew WatermanRefactor memory access code; add MMIO support
2015-09-25 Andrew WatermanUse enum instead of two bools to denote memory access...
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-26 Andrew WatermanFix I$ simulator hit count
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-14 Andrew WatermanDon't set dirty/referenced bits w/o permission
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2015-01-02 Andrew WatermanReduce dependences on auto-generated code
2014-12-05 Andrew WatermanSet badvaddr on instruction page faults
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-02-15 Andrew Watermandon't store host pointers in soft TLB
2013-02-13 Andrew Watermanclean up fetch-execute loop a bit
2013-02-13 Andrew Watermanadd I$/D$/L2$ simulators
2012-03-24 Andrew Watermannew supervisor mode
2012-01-31 Andrew Watermandon't set badvaddr for instruction access faults
2012-01-24 Andrew Watermancheck that virtual addresses are sign-extended
2011-11-01 Andrew WatermanFixed tight coupling of host and target page size
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] tlb now stores host addresses
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support