| 2016-06-23 |
Andrew Waterman | Remove legacy HTIF; implement HTIF directly |
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| 2016-06-23 |
Andrew Waterman | Fix paddr_bits computation prior to VM setup |
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| 2016-06-18 |
Andrew Waterman | Merge sasid into sptbr |
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| 2016-06-09 |
Andrew Waterman | Trap on tdrdata registers when tdrselect[XLEN-1]=0 |
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| 2016-06-09 |
Andrew Waterman | Add degenerate HW breakpoint implementation |
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| 2016-05-23 |
Tim Newsome | Turn off debugging. |
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| 2016-05-23 |
Tim Newsome | Tell gdb we can handle large packets. |
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| 2016-05-23 |
Tim Newsome | Exceptions in Debug Mode don't update any regs. |
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| 2016-05-23 |
Tim Newsome | Remove already-implemented TODO. |
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| 2016-05-23 |
Tim Newsome | Implement ebreak[mhsu]. |
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| 2016-05-23 |
Tim Newsome | Remove dependency on include file in my homedir. |
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| 2016-05-23 |
Tim Newsome | Make -H halt the core right out of reset. |
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| 2016-05-23 |
Tim Newsome | Halt when gdb user hits ^C. |
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| 2016-05-23 |
Tim Newsome | Single step appears to work. |
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| 2016-05-23 |
Tim Newsome | Fix off-by-two in general read registers. |
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| 2016-05-23 |
Tim Newsome | Remove unused code. |
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| 2016-05-23 |
Tim Newsome | Add dret. |
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| 2016-05-23 |
Tim Newsome | Implement single memory read access. |
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| 2016-05-23 |
Tim Newsome | Exceptions in Debug Mode, stay in Debug Mode. |
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| 2016-05-23 |
Tim Newsome | Continue works well enough for DebugTest.test_exit |
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| 2016-05-23 |
Tim Newsome | Refactor how we track in-progress operations. |
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| 2016-05-23 |
Tim Newsome | processor_t unfriends gdbserver_t. |
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| 2016-05-23 |
Tim Newsome | Add debug_module bus device. |
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| 2016-05-23 |
Tim Newsome | Can jump to and execute Debug ROM. |
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| 2016-05-23 |
Tim Newsome | When gdb connects, jump to Debug ROM and segfault. |
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| 2016-05-23 |
Tim Newsome | Gutting direct-access gdb. |
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| 2016-05-23 |
Tim Newsome | Add writing to DCSR, DPC, DSCRATCH. |
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| 2016-05-23 |
Tim Newsome | Only halt on ebreak if a debugger is attached. |
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| 2016-05-23 |
Tim Newsome | Flush icache when using swbps and report to gdb. |
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| 2016-05-23 |
Tim Newsome | Software breakpoints seem to work. |
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| 2016-05-23 |
Tim Newsome | Looks like single step works. |
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| 2016-05-23 |
Tim Newsome | Now you can halt/continue from gdb. |
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| 2016-05-22 |
Andrew Waterman | Allow delegation of device interrupts |
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| 2016-05-02 |
Andrew Waterman | Add back IPI support |
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| 2016-05-02 |
Andrew Waterman | Remove MIPI; mip.MSIP bit is read-only |
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| 2016-05-02 |
Andrew Waterman | Remove tohost/fromhost registers |
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| 2016-05-01 |
Andrew Waterman | Initialize mtvec to DEFAULT_MTVEC |
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| 2016-05-01 |
Andrew Waterman | Remove SCRs; add padding after config string |
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| 2016-04-29 |
Andrew Waterman | Move much closer to new platform-M memory map |
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| 2016-04-28 |
Andrew Waterman | Remove MTIME[CMP]; add RTC device |
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| 2016-04-06 |
Andrew Waterman | Remove non-standard uarch CSRs |
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| 2016-03-17 |
Andrew Waterman | Update definition of base field in misa register |
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| 2016-03-04 |
Andrew Waterman | Fix up interrupt delegation |
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| 2016-03-02 |
Andrew Waterman | Add counter-enable registers |
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| 2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
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| 2016-03-02 |
Andrew Waterman | New definitions of misa/marchid/mvendorid |
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| 2016-03-02 |
Andrew Waterman | implement PUM functionality |
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| 2016-03-02 |
Andrew Waterman | sptbr now a holds a PPN, not an address |
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| 2016-03-02 |
Andrew Waterman | Use simpler MTVEC scheme |
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| 2016-03-02 |
Andrew Waterman | Zero-extend all CSR writes |
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| 2016-03-02 |
Andrew Waterman | Fix ERET serialization strategy |
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| 2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
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| 2016-01-13 |
Andrew Waterman | don't ignore data value when writing MIPI |
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| 2015-11-13 |
Andrew Waterman | Generate device tree for target machine |
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| 2015-10-26 |
Andrew Waterman | Fix histogram for RVC |
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| 2015-09-11 |
Andrew Waterman | Simplify register_base_instructions |
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| 2015-09-11 |
Andrew Waterman | Initialize mstatus.prv1/prv2 to U, not S |
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| 2015-09-11 |
Andrew Waterman | Support 'G' in ISA strings |
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| 2015-09-09 |
Andrew Waterman | Improve instruction fetch |
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| 2015-07-30 |
Christopher Celio | Added error message when trying to use histogram |
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| 2015-07-05 |
Andrew Waterman | New machine-mode timer facility |
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| 2015-06-01 |
Andrew Waterman | Use single, shared real-time counter |
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| 2015-06-01 |
Andrew Waterman | Execute exactly the # of insns passed to step() |
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| 2015-06-01 |
Andrew Waterman | Fix performance bug when CSR accesses are common |
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| 2015-06-01 |
Andrew Waterman | Take interrupts as soon as interrupts are enabled |
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| 2015-05-09 |
Andrew Waterman | Upgrade to privileged architecture 1.7 |
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| 2015-04-30 |
Andrew Waterman | Fix commit log for CSR instructions |
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| 2015-04-04 |
Andrew Waterman | Check for F extension when accessing FCSR |
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| 2015-04-04 |
Andrew Waterman | Support setting ISA/subsets with --isa flag |
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| 2015-03-31 |
Andrew Waterman | Allow writing mstatus.fs even if FPU isn't present |
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| 2015-03-27 |
Andrew Waterman | Serialize counters without throwing C++ exceptions |
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| 2015-03-26 |
Andrew Waterman | Update state.pc on every instruction |
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| 2015-03-17 |
Yunsup Lee | bugfix, mbadaddr should be writable |
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| 2015-03-13 |
Andrew Waterman | Update to new privileged spec |
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| 2015-01-27 |
Christopher Celio | Fixed masking/casting logic in commit log printf. |
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| 2015-01-26 |
Andrew Waterman | Fix commit log |
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| 2015-01-02 |
Andrew Waterman | Reduce dependences on auto-generated code |
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| 2014-12-05 |
Andrew Waterman | Support 2/4/6/8-byte instructions |
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| 2014-12-01 |
Andrew Waterman | Implement timer faithfully |
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| 2014-08-15 |
Christopher Celio | Added PC histogram option. |
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| 2014-08-08 |
Andrew Waterman | Support uarch counters (degenerately) |
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| 2014-07-08 |
Andrew Waterman | Disallow access to FCSR when FP is disabled |
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| 2014-07-07 |
Andrew Waterman | Minor refactoring |
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| 2014-06-13 |
Christopher Celio | Commit log now prints while interrupts are enabled. |
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| 2014-06-13 |
Andrew Waterman | Only print commit log if instruction commits |
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| 2014-06-12 |
Andrew Waterman | Set status.u64 to true on boot |
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| 2014-04-03 |
Stephen Twigg | Merge branch 'tm' |
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| 2014-03-18 |
Andrew Waterman | Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH |
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| 2014-03-15 |
Andrew Waterman | speed up compilation a bit |
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| 2014-02-14 |
Andrew Waterman | Fix I$ simulator not making forward progress |
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| 2014-02-12 |
Andrew Waterman | Fix commit log when !debug |
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| 2014-02-07 |
Andrew Waterman | Clear EVEC LSBs, which kindly prevents a segfault |
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| 2014-01-24 |
Andrew Waterman | Handle CSR permissions correctly |
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| 2014-01-21 |
Quan Nguyen | Merge branch 'confprec' |
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| 2014-01-16 |
Andrew Waterman | Initialize tohost and fromhost to zero |
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| 2014-01-14 |
Andrew Waterman | Improve performance for branchy code |
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| 2013-12-17 |
Andrew Waterman | Speed things up quite a bit |
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| 2013-11-25 |
Andrew Waterman | Update to new privileged ISA |
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| 2013-11-05 |
Albert Ou | Merge branch 'master' of github.com:ucb-bar/riscv-isa... |
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| 2013-10-19 |
Yunsup Lee | clean up SR_EA, the enable accelerator bit in status reg |
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