| 2017-04-18 |
Megan Wachs | debug: Checkpoint which somewhat works with OpenOCD... |
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| 2017-04-18 |
Megan Wachs | debug: Move things around, but addresses now conflict... |
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| 2017-04-17 |
Megan Wachs | Merge remote-tracking branch 'origin/priv-1.10' into... |
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| 2017-04-11 |
Andrew Waterman | Implement new FP encoding |
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| 2017-03-28 |
Andrew Waterman | Set badaddr=0 on illegal instruction traps |
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| 2017-03-23 |
Andrew Waterman | Require little-endian host |
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| 2017-02-21 |
Andrew Waterman | serialize simulator on wfi |
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| 2017-02-13 |
Tim Newsome | Abstract register read mostly working. |
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| 2017-02-11 |
Tim Newsome | Entering debug mode now jumps to "dynamic rom" |
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| 2016-06-01 |
Tim Newsome | Move sethaltnot and cleardebint. |
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| 2016-05-24 |
Tim Newsome | Move cleardebint, per spec. |
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| 2016-05-23 |
Tim Newsome | Remove dependency on include file in my homedir. |
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| 2016-05-23 |
Tim Newsome | Software breakpoints sort of work. |
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| 2016-05-23 |
Tim Newsome | Exceptions in Debug Mode, stay in Debug Mode. |
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| 2016-05-23 |
Tim Newsome | Have Debug memory kind of working again. |
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| 2016-05-23 |
Tim Newsome | Add debug_module bus device. |
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| 2016-05-23 |
Tim Newsome | Make sure to translate Debug RAM addresses also. |
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| 2016-05-23 |
Tim Newsome | Clean up how Debug ROM is included. |
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| 2016-05-23 |
Tim Newsome | Can jump to and execute Debug ROM. |
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| 2016-05-23 |
Tim Newsome | When gdb connects, jump to Debug ROM and segfault. |
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| 2016-05-23 |
Tim Newsome | Gutting direct-access gdb. |
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| 2016-05-23 |
Tim Newsome | Add writing to DCSR, DPC, DSCRATCH. |
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| 2016-05-21 |
Andy Wright | Some bugfixes for CSR reading and setting FS for fflags... |
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| 2016-03-02 |
Andrew Waterman | Fix ERET serialization strategy |
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| 2016-03-02 |
Andrew Waterman | Serialize simulator on ERET |
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| 2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
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| 2016-03-02 |
Andrew Waterman | Upgrade to latest SoftFloat |
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| 2015-11-13 |
Andrew Waterman | Generate device tree for target machine |
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| 2015-11-13 |
Andrew Waterman | Access FP regs through a macro |
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| 2015-10-06 |
Andrew Waterman | more work towards RVC 1.8 |
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| 2015-10-02 |
Andrew Waterman | work towards rvc 1.8 |
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| 2015-09-09 |
Andrew Waterman | Improve instruction fetch |
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| 2015-09-04 |
Andrew Waterman | Move towards RVC v1.8 |
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| 2015-06-01 |
Andrew Waterman | Add rest of RV32C instructions |
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| 2015-06-01 |
Andrew Waterman | New RV64C proposal |
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| 2015-04-04 |
Andrew Waterman | Support setting ISA/subsets with --isa flag |
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| 2015-04-02 |
Andrew Waterman | Simplify RV32 comparisons |
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| 2015-03-31 |
Andrew Waterman | Allow writing mstatus.fs even if FPU isn't present |
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| 2015-03-31 |
Andrew Waterman | Implement RVC draft |
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| 2015-03-27 |
Andrew Waterman | Serialize counters without throwing C++ exceptions |
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| 2015-03-21 |
Andrew Waterman | For misaligned fetch, set mepc = addr of branch/jump |
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| 2015-03-13 |
Andrew Waterman | Update to new privileged spec |
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| 2015-02-08 |
Andrew Waterman | Use xlen, not xprlen, to refer to x-register width |
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| 2015-01-26 |
Andrew Waterman | Fix commit log |
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| 2015-01-03 |
Andrew Waterman | On misaligned fetch, set EPC to target, not branch... |
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| 2014-12-05 |
Andrew Waterman | Support 2/4/6/8-byte instructions |
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| 2014-12-05 |
Andrew Waterman | Set badvaddr on instruction page faults |
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| 2014-12-01 |
Andrew Waterman | Implement timer faithfully |
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| 2014-09-27 |
Andrew Waterman | Avoid use of __int128_t |
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| 2014-07-08 |
Andrew Waterman | Disallow access to FCSR when FP is disabled |
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| 2014-06-13 |
Christopher Celio | Commit log now prints while interrupts are enabled. |
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| 2014-06-13 |
Andrew Waterman | Only print commit log if instruction commits |
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| 2014-01-24 |
Andrew Waterman | Handle CSR permissions correctly |
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| 2014-01-21 |
Quan Nguyen | Merge branch 'confprec' |
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| 2014-01-14 |
Andrew Waterman | Improve performance for branchy code |
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| 2013-12-17 |
Andrew Waterman | Speed things up quite a bit |
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| 2013-12-09 |
Andrew Waterman | New RDCYCLE encoding |
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| 2013-11-25 |
Andrew Waterman | Update to new privileged ISA |
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| 2013-11-25 |
Quan Nguyen | Merge branch 'master' of github.com:ucb-bar/riscv-isa... |
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| 2013-11-06 |
Yunsup Lee | correctly trap when SR_EA is disabled |
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| 2013-09-27 |
Christopher Celio | Added commit logging (--enable-commitlog). Also fixed... |
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| 2013-09-27 |
Andrew Waterman | Use WRITE_RD/WRITE_FRD macros to write registers |
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| 2013-09-21 |
Andrew Waterman | Update ISA encoding and AUIPC semantics |
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| 2013-09-11 |
Andrew Waterman | Implement zany immediates |
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| 2013-09-10 |
Andrew Waterman | Add rd field to JAL; drop J |
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| 2013-08-12 |
Andrew Waterman | Instructions are no longer member functions |
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| 2013-08-08 |
Andrew Waterman | Disentangle some header files |
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| 2013-07-27 |
Andrew Waterman | Remove more vector stuff |
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| 2013-07-26 |
Andrew Waterman | Rip out RVC for now |
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| 2013-07-26 |
Andrew Waterman | Generate instruction decoder dynamically |
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| 2013-04-24 |
Yunsup Lee | fixes to correctly simulate the vector unit |
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| 2013-03-26 |
Andrew Waterman | add BSD license |
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| 2013-03-26 |
Andrew Waterman | truncate effective addresses in rv32 |
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| 2013-03-26 |
Andrew Waterman | support compilation with gcc 4.7 |
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| 2013-01-26 |
Andrew Waterman | change htif to link against libfesvr |
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| 2012-03-24 |
Andrew Waterman | new supervisor mode |
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| 2012-03-20 |
Andrew Waterman | abstract regfile write port |
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| 2012-03-20 |
Andrew Waterman | abstract regfile behind object |
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| 2012-01-23 |
Andrew Waterman | disentangle decode.h from other headers |
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| 2012-01-23 |
Andrew Waterman | work around gcc 4.4 bug |
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| 2011-11-11 |
Andrew Waterman | Changed supervisor mode |
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| 2011-06-20 |
Andrew Waterman | temporary undoing of renaming |
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| 2011-06-13 |
Andrew Waterman | [sim] renamed to riscv-isa-run |
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| 2011-06-12 |
Andrew Waterman | [xcc] minor performance tweaks |
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| 2011-06-11 |
Andrew Waterman | [xcc] instructions now set PC explicitly |
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| 2011-05-29 |
Andrew Waterman | [sim,opcodes] improved sim build and run performance |
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| 2011-05-29 |
Andrew Waterman | [fesvr,xcc,sim] fixed multicore sim for akaros |
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| 2011-05-18 |
Yunsup Lee | [opcodes,pk,sim] add more vector traps (for #banks... |
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| 2011-05-14 |
Andrew Waterman | [sim] initial support for virtual memory |
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| 2011-04-24 |
Andrew Waterman | [xcc,sim,opcodes] added more RVC instructions |
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| 2011-04-19 |
Andrew Waterman | [xcc,sim,opcodes] added rvc conditional branches |
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| 2011-04-17 |
Andrew Waterman | [sim] removed undefined behavior for non-canonical... |
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| 2011-04-13 |
Andrew Waterman | [xcc,sim] fixed RM field |
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| 2011-04-12 |
Andrew Waterman | [xcc,sim] rvc loads and stores |
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| 2011-04-12 |
Andrew Waterman | [sim] fixed FSR exception field bug |
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| 2011-04-12 |
Andrew Waterman | [xcc,sim,opcodes] more rvc instructions and bug fixes |
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| 2011-04-10 |
Yunsup Lee | [sim] add vt stuff |
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| 2011-04-10 |
Andrew Waterman | [sim,pk] reorganized status register |
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| 2011-04-10 |
Andrew Waterman | [xcc,pk,sim,opcodes] added first RVC instruction |
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| 2011-03-01 |
Andrew Waterman | [xcc,sim] branches are pc-relative (not pc+4) again |
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