Enforce 2-byte alignment of mepc/sepc/dpc
[riscv-isa-sim.git] / riscv / processor.cc
2018-03-03 Andrew WatermanEnforce 2-byte alignment of mepc/sepc/dpc
2018-02-19 Tim NewsomeMerge pull request #171 from riscv/sysbusbits
2018-02-13 Andrew WatermanImplement cycleh/instreth CSRs for RV32 (#172)
2017-11-27 Andrew WatermanRename badaddr to tval
2017-11-27 Andrew WatermanRename sptbr to satp
2017-11-27 Andrew WatermanSet tval to 0 on traps with no specified tval
2017-11-20 Andrew WatermanImplement priv-1.11 interrupt-priority scheme (#161)
2017-11-16 Andrew WatermanMerge pull request #156 from p12nGH/noncontiguous_harts
2017-11-10 Andrew WatermanRemove redundant U/S mode advertisement
2017-11-10 Andrew WatermanH-mode no longer exists
2017-11-10 Andrew WatermanMPP is now WARL
2017-11-03 Andrew WatermanMask medeleg correctly
2017-11-02 Andrew WatermanDon't permit delegation of interrupts that M-mode shoul...
2017-10-11 Andrew WatermanMerge pull request #129 from riscv/q-extension
2017-09-28 Andrew WatermanImplement Q extension
2017-09-21 Tim NewsomeFix corner case in repeated execution (#127)
2017-09-12 Tim NewsomeMerge pull request #123 from riscv/debug_interrupts
2017-09-12 Tim NewsomeDon't take interrupts while in Debug Mode.
2017-08-10 Tim NewsomeMerge pull request #117 from riscv/multicore_debug
2017-08-07 Tim NewsomeFix multicore debug.
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-05-16 Palmer DabbeltMerge remote-tracking branch 'origin/debug-0.13' into...
2017-05-15 Megan WachsMerge branch 'debug-0.13' into HEAD
2017-05-05 Andrew WatermanUXL=SXL=MXL
2017-04-26 Palmer DabbeltMerge pull request #96 from riscv/ndmreset
2017-04-26 Palmer DabbeltRemove a debugging printf
2017-04-18 Megan Wachsdebug: Checkpoint which somewhat works with OpenOCD...
2017-04-18 Megan Wachsdebug: Move things around, but addresses now conflict...
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-04-08 Andrew WatermanImplement vectored interrupt proposal
2017-03-28 Andrew WatermanSet badaddr=0 on illegal instruction traps
2017-03-21 Wesley W. Terpstrariscv: remove dependency on num_cores
2017-03-20 Andrew WatermanPUM -> SUM; expose MXR to S-mode
2017-03-16 Andrew WatermanSimplify interrupt-stack discipline
2017-03-13 Andrew WatermanImplement mstatus.TW, mstatus.TVM, and mstatus.TSR
2017-02-27 Andrew WatermanSv57 and Sv64 are not spec'd yet
2017-02-25 Andrew WatermanNew counter enable scheme
2017-02-23 Tim NewsomeImplement halt request.
2017-02-21 Andrew WatermanTake M-mode interrupts over S-mode interrupts
2017-02-21 Andrew Watermanpermit MMIO loads to MSIP bit
2017-02-18 Andrew WatermanSpike uarch needs TLB flush after SPTBR write
2017-02-18 Tim NewsomeCompress log output of jump-to-self loops.
2017-02-13 Tim NewsomeAbstract register read mostly working.
2017-02-11 Tim NewsomeEntering debug mode now jumps to "dynamic rom"
2017-02-10 Tim NewsomeRemove gdbserver support.
2017-02-08 Andrew WatermanEncode VM type in sptbr, not mstatus
2017-02-07 Tim NewsomeMerge pull request #83 from bacam/gdb-protocol-fixes
2017-02-03 Andrew WatermanFix interrupt delegation for coprocessors
2017-01-08 Andrew WatermanOnly allow SIP.SSIP to be toggled if the interrupt...
2017-01-08 Andrew WatermanMake SIP.STIP read-only
2016-10-10 Andrew WatermanDon't force load trigger timing to After
2016-09-29 Tim NewsomeUpdate trigger behavior. (#70)
2016-09-10 Andrew Watermanallow MAFDC bits in MISA to be modified
2016-09-02 Andrew WatermanMerge pull request #62 from riscv/trigger
2016-09-02 Tim NewsomeMerge branch 'master' into trigger
2016-09-01 Tim NewsomeTheoretically support trigger timing.
2016-08-31 Tim NewsomeRename tdata[0-2] to tdata[1-3].
2016-08-29 Tim NewsomeRename tdata0--tdata2 to tdata1--tdata3.
2016-08-27 Andrew WatermanAdd (degenerate) performance counter facility
2016-08-26 Andrew WatermanAllow reads from tdrdata registers
2016-08-26 Andrew Watermanpartially update spike to newer debug spec
2016-08-26 Andrew WatermanFix spike interactive (-d) mode
2016-08-23 Andrew Watermanremove HWBPCOUNT field of DCSR
2016-08-22 Tim NewsomeImplement address and data triggers.
2016-08-17 Andrew WatermanAllow mstatus.MPP to store bad values; instead, validat...
2016-07-28 Tim NewsomeAdd support for virtual priv register. (#59)
2016-07-22 Andrew WatermanSet U bit in misa register
2016-07-12 Andrew WatermanDon't treat RVC NOP as illegal instruction
2016-07-06 Andrew WatermanUpdate to new PTE format
2016-06-29 Andrew WatermanDisassemble RVC instructions based on XLEN
2016-06-23 Andrew WatermanRemove legacy HTIF; implement HTIF directly
2016-06-23 Andrew WatermanFix paddr_bits computation prior to VM setup
2016-06-18 Andrew WatermanMerge sasid into sptbr
2016-06-09 Andrew WatermanTrap on tdrdata registers when tdrselect[XLEN-1]=0
2016-06-09 Andrew WatermanAdd degenerate HW breakpoint implementation
2016-05-23 Tim NewsomeTurn off debugging.
2016-05-23 Tim NewsomeTell gdb we can handle large packets.
2016-05-23 Tim NewsomeExceptions in Debug Mode don't update any regs.
2016-05-23 Tim NewsomeRemove already-implemented TODO.
2016-05-23 Tim NewsomeImplement ebreak[mhsu].
2016-05-23 Tim NewsomeRemove dependency on include file in my homedir.
2016-05-23 Tim NewsomeMake -H halt the core right out of reset.
2016-05-23 Tim NewsomeHalt when gdb user hits ^C.
2016-05-23 Tim NewsomeSingle step appears to work.
2016-05-23 Tim NewsomeFix off-by-two in general read registers.
2016-05-23 Tim NewsomeRemove unused code.
2016-05-23 Tim NewsomeAdd dret.
2016-05-23 Tim NewsomeImplement single memory read access.
2016-05-23 Tim NewsomeExceptions in Debug Mode, stay in Debug Mode.
2016-05-23 Tim NewsomeContinue works well enough for DebugTest.test_exit
2016-05-23 Tim NewsomeRefactor how we track in-progress operations.
2016-05-23 Tim Newsomeprocessor_t unfriends gdbserver_t.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeCan jump to and execute Debug ROM.
2016-05-23 Tim NewsomeWhen gdb connects, jump to Debug ROM and segfault.
2016-05-23 Tim NewsomeGutting direct-access gdb.
2016-05-23 Tim NewsomeAdd writing to DCSR, DPC, DSCRATCH.
2016-05-23 Tim NewsomeOnly halt on ebreak if a debugger is attached.
2016-05-23 Tim NewsomeFlush icache when using swbps and report to gdb.
2016-05-23 Tim NewsomeSoftware breakpoints seem to work.
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